characterization, modeling, and design of esd protection circuits

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EECF/EECNS and by Fely Barrera and Maria Perea. To the other members of the TCADre, I have not forgotten you and will often reminisce on those three characterbuilding softball seasons which taught us that victory is sweeter when tasted less often. vi
Contents Abstract iii Acknowledgments v List of Figures xi List of Tables xvi 1 Introduction 1 1.1 ESD in the Integrated Circuit Industry . . . . . . . . . . . . . . . . . . . . . 3 1.2 Characterizing ESD in Integrated Circuits . . . . . . . . . . . . . . . . . . . 4 1.3 Protecting Integrated Circuits from ESD . . . . . . . . . . . . . . . . . . . . 6 1.4 Numerical Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6 Outline and Contributions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 ESD Circuit Characterization and Design Issues 15 2.1 Classical ESD Characterization Models and Industrial Testing . . . . . . . . 16 2.2 Transmission Line Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 MOSFET Snapback I-V Curve . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 Failure Power vs. Time to Failure. . . . . . . . . . . . . . . . . . . . 29 2.2.3 Leakage Current Evolution . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.4 Advanced TLP Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 Overview of Protection Circuit Design . . . . . . . . . . . . . . . . . . . . . 37 2.4 Dependence of Critical MOSFET I-V Parameters on Process and Layout . . . 44 2.5 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 vii
Page 1 and 2: CHARACTERIZATION, MODELING, AND DES
Page 3 and 4: Abstract For more than 20 years, su
Page 5: Acknowledgments This work could not
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 55 and 56: 2.3. Overview of Protection Circuit
Page 57 and 58:
2.3. Overview of Protection Circuit
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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Page 99 and 100:
Page 101 and 102:
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3.7. Simulation of Dielectric Failu
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Page 107 and 108:
Page 109 and 110:
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
Page 217 and 218:
Bibliography 201 [20] C. Duvvury, R
Page 219 and 220:
Bibliography 203 [42] S.M. Sze, Phy
Page 221 and 222:
Bibliography 205 [63] R. van Overst
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