characterization, modeling, and design of esd protection circuits

72 Chapter 3. Simulation: Methods and Applications
methodology “may be used to achieve a successful first-pass design” and that device
simulations are useful for determining qualitative relationships such as the effect of the
npn junction capacitances on the trigger voltage.
Use of 2D device simulation in predicting ESD robustness was studied by Amerasekera et
al. [32], who investigated the use of simulated peak power density ( ), peak
temperature, and second-breakdown trigger current, It2 , as relative figures of merit of
MOS devices with various source/drain profiles, contact-to-gate spacings, and gate
biasing. A Texas Instruments in-house electrothermal simulator was used to generate dc
curves which exhibited snapback and, surprisingly, second breakdown (a drop in device
voltage due to thermal runaway is usually not observed in 2D dc simulations due to the 3D
nature of the phenomenon). Thermal electrodes with a lumped resistance of 10 6 J ⋅ E
K/W were
placed on each of the four electrical contacts. The authors found that reaching a critical
temperature is a better figure of merit than reaching a critical J ⋅
E because the peak
electric field is very dependent on the simulation grid, which is different for different
structures. Using simulated It2 as a failure criteria was found to agree qualitatively with
experiments of varying drain junction profiles and to agree quantitatively with
experimental It2 vs. gate bias. On the other hand, simulated It2 did not increase with drain
contact-to-gate spacing as it does in experiment, leading the authors to conclude that it is
not possible to model the effect of some layout parameters on ESD robustness because the
simulation is only two dimensional. It is important to note, however, that they are looking
at dc results, i.e., EOS, not ESD. Since ESD events are very brief, the effects of thermal
diffusion in the width dimension may not have an impact on the device robustness and no
conclusions should be drawn from dc simulations on modeling the ESD regime.
Transient simulations were also run with constant-current pulses used as the ESD input. A
good fit of transient simulation points to an experimental Pf vs. tf curve between 25ns and
200ns of a 0.6µm device was obtained by defining failure as the time at which the peak
temperature reaches 1000K. (Experimentally, failure is the point at which a device enters
second breakdown.) The analytic thermal model (Section 2.2.2) was also fit to the data
using a Tc of 1000K and box dimensions of c = 0.5µm, b = 0.5µm, and a = device width.
The good agreement of the Pf vs. tf results led the authors to conclude that “the concept of
a critical temperature for (thermal) breakdown is valid for the devices investigated in this
study.”