characterization, modeling, and design of esd protection circuits

48 Chapter 2. ESD Circuit Characterization and Design Issues
voltage, VT [41]. The reduction in Vt1 ranges from a few volts for small gate-length
devices to about 50% for larger gate lengths. Beyond VT , the trigger voltage levels off
with increased gate biasing and may actually increase since the reduced electric field in
the drain depletion region will reduce impact ionization. If the gate remains biased after
a device has entered snapback, It2 can be reduced due to concentration of drain-source
current at the surface of the channel, so it is important that the gate be biased only
during initial turn-on of the device.
• LDD -- It is generally assumed that a lightly doped drain decreases the performance of
an ESD protection structure because it has a much lower junction depth than the S/D
diffusion, which leads to higher current concentrations in the area of high electric field
(i.e., the box depth is smaller in the 3D thermal model) and thus reduces It2 . However,
if the LDD depth is not much different than the S/D depth, then there should be little
change in It2 unless the accompanying change in the electric-field profile is significant.
In a CMOS process the NMOS LDD implant can be blocked simply by covering the
NMOS active area with the same oxide used to mask the PMOS active areas during this
implant. Of course, the spacer oxide will still be present after the oxide etch, which
means the S/D diffusion edges will be separated from the intrinsic channel under the
gate contact, i.e., the gate length is effectively increased by twice the spacer width.
(Since it is only the drain side of the device which has the high electric field, the source
LDD diffusion may be left in the process, meaning the gate length is only increased by
one spacer width.) Thus, blocking the LDD implant also effects the same changes as
increasing the gate length. These effects may be compensated by reducing the drawn
gate length. Although the drain junction may become more abrupt when the LDD is
omitted, Vbd increases because the net drain doping decreases without the LDD
implant, and therefore Vt1 and Vsb also increase. The snapback resistance will also
probably be slightly larger due to the increased effective gate length.
• Substrate resistance -- Increasing the substrate resistance, either by moving the substrate
contact farther away from the drain diffusion or by adding a lumped resistance
between the local substrate contact and ground, or floating the substrate accelerates the
onset of snapback by creating a higher substrate bias for the same substrate current and
by diverting more of the impact-ionization generated holes toward the source to forward
bias the source-substrate junction. The reduction in Vt1 and It1 imply a faster triggering
of the device. To first order, the snapback region of operation is not affected by