characterization, modeling, and design of esd protection circuits

170 Chapter 6. Conclusion
6.2.2 Modeling
As shown by the results of Chapter 4, simulations may actually provide a more useful
method for studying ESD-circuit turn-on time because good agreement between simulated
and measured low-current snapback parameters was demonstrated. Of greater concern is
the ability to simulate the high-current portion of the MOSFET snapback curve and the
onset of thermal failure. It was found that some of the assumptions of the calibration
procedure were incorrect. Calibration of mobility and impact ionization using only
standard room-temperature MOSFET characteristics is not adequate for simulation of
ESD phenomena above the point of snapback. One procedure which was not attempted
was the calibration of MOSFET characteristics at higher temperatures. Even if data and
simulations are only examined up to 250 o C, proper calibration will aid the prevention of
the exaggerated increase in snapback resistance observed in present simulations. It may
also be worthwhile to measure the temperature-dependent thermal resistance and
capacitance of the silicon material to ensure the corresponding simulator models are
accurate. Regardless, the most critical issue which must be addressed is the effect of
simulation grid on the electric field profile, which was shown to be the main obstruction of
proper high-current impact-ionization modeling.
Limitations of 2D device simulation also need to be further quantified. Although the
difference between 2D and 3D thermal models was studied, the implications of this study
remain unclear due to the incomplete thermal-failure calibration and the deviation of the
boundary conditions in a real MOSFET structure from the assumptions of the model.
Another concern for future simulations is the validity of the assumption that the electron
and hole temperatures are in thermal equilibrium with the lattice. As discussed in Chapter
3, as electric fields increase due to smaller device dimensions and greater stress, hot
carrier effects will become more important. During extremely brief, high-field ESD events
such as CDM stress, carriers may no longer be in equilibrium with the lattice and full twocarrier-plus-lattice-temperature
modeling, such as offered by PISCES-2ET (dual energy
transport model), will be needed. Such modeling would require calibration of different
mobility and impact ionization models which are dependent on carrier temperature.
Another type of modeling which was not studied in this thesis is compact modeling, i.e.,
circuit-level or SPICE-level modeling. For ESD simulation, compact modeling is
especially useful for determining current paths in circuits subjected to ESD stress.