characterization, modeling, and design of esd protection circuits

204 Bibliography
[53] S. Tam, P.-K. Ko, and C. Hu, “Lucky-Electron Model of Channel Hot-Electron
Injection in MOSFETs,” IEEE Trans. Elec. Dev., vol. ED-31, 1984, pp. 1116-1125.
[54] B.S. Doyle, D.B. Krakauer, and K.R. Mistry, “Examination of Oxide Damage
During High-Current Stress of n-MOS Transistors,” IEEE Trans. Elec. Dev., vol.
ED-40, 1993, pp. 980-985.
[55] H. Haddara and S. Cristoloveanu, “Two-dimensional modeling of locally damaged
short-channel MOSFETs operating in the linear region,” IEEE Trans. Elec. Dev.,
vol. ED-34, 1987, pp. 378-385.
[56] A. Schwerin, W. Hansch, and W. Weber, “The relationship between oxide charge and
device degradation: A comparative study of n- and p-channel MOSFETs,” IEEE
Trans. Elec. Dev., vol. ED-34, 1987, pp. 2493-2500.
[57] S.H. Voldman and V.P. Gross, “Scaling, Optimization and Design Considerations of
Electrostatic Discharge Protection Circuits in CMOS Technology,” Proc. 15th
EOS/ESD Symp., 1993, pp. 251-260.
[58] G. Kreiger, “ESD in Integrated Circuits--General Introduction,” ESD in Integrated
Circuits Short Course Proceedings, sponsored by University of California,
Berkeley, 1992.
[59] M.E. Law, C.S. Rafferty, and R.W. Dutton, “SUPREM-IV Users Manual,” Integrated
Circuits Laboratory, Stanford University, 1988.
[60] C.D. Thurmond, “The Standard Thermodynamic Function of the Formation of
Electrons and Holes in Ge, Si, GaAs and GaP,” J. Electrochem. Soc., vol. 122,
1975, pp. 1133-1141.
[61] R.S. Muller and T.I. Kamins, Device Electronics for Integrated Circuits, 2nd Ed.,
John Wiley, New York, 1986.
[62] C. Jacoboni, C. Canali, G. Ottaviani, and A.A. Quaranta, “A Review of Some Charge
Transport Properties of Silicon,” Solid-State Electronics, vol. 20, 1977, pp. 77-89.