characterization, modeling, and design of esd protection circuits

2.3. Overview of Protection Circuit Design 43
Bond pad
V CC
M1 Rdiff M2
Input
VSS Fig. 2.18 Combination resistor/transistor ESD input protection circuit, featuring a
diffused resistor (Rdiff ) between wide (M1) and narrow (M2) NMOS
transistors. Resistance from gate to ground is not shown.
in Fig. 2.18. The narrow transistor is designed with a minimal gate length so that its
parasitic bipolar transistor will turn on quickly and clamp the input voltage during a short
ESD event. During a longer event the wide transistor, which may have a longer gate length
and turn-on time, absorbs the majority of ESD current. The well resistor creates a voltage
drop which ensures that the drain voltage of the wide transistor will build up to the
breakdown value instead of being clamped at Vsb of the narrow transistor. This circuit
only begins to suggest the creativity that can be used in designing protection circuits, but it
exemplifies the implementation of different devices to provide protection across a broad
range of the EOS/ESD spectrum.
In closing out this section on ESD circuits, it should be mentioned that a CMOS I/O
protection transistor usually consists of several “fingers” of devices in parallel coming off
an I/O pad rather than a single, very wide MOSFET (Fig. 2.19). This design method is
used because ESD-current robustness increases with device width and multiple fingers
furnish a compact way of providing a large effective width on a circuit in which space is at
a premium. Also, a single narrow metal finger coming off of the contact pad will have a
higher current density than several fingers in parallel and thus will be more susceptible to
damage. One important drawback of such “multifingered” devices is that due to random
variations between fingers it is almost never the case that all fingers of a protection device
will turn on simultaneously during an ESD event. Instead, after one device breaks down
and quickly enters the snapback mode, the drain voltage of all the devices is clamped at
the snapback voltage since they are all tied to the input. As the current increases, the