characterization, modeling, and design of esd protection circuits

2.5. Design Methodology 49
the substrate resistance. However, It2 will be reduced, especially if the substrate is floating,
because the reduced fraction of stress current sunk by the substrate implies a higher
concentration of current underneath the gate and thus more device heating.
2.5 Design Methodology
An ESD circuit design methodology should be based on the goal of robust protection from
thermal and dielectric failure across a wide range of the EOS/ESD spectrum. In today’s
environment an IC manufacturer will probably want to guarantee that its packaged devices
will perform within specifications after any pins are subjected to some voltage level of the
HBM test and possibly of the CDM test because these are the standard ways of measuring
ESD robustness. However, it is important to use a broad-range testing method such as TLP
to ensure ESD protection not only for specific tests but for any potential stress which can
lead to a field failure or customer return. The design methodology presented in this work
focuses on multifinger CMOS protection circuits for IC inputs and outputs; this section
emphasizes optimization of the individual devices (fingers) before creating and testing the
overall circuit. Design and optimization of multifinger circuits is the main topic of Chapter
5. Although ESD circuits are definitely susceptible to failure at contacts, diffused resistors,
poly resistors, and other interconnect sites due to excessive heating, this design process is
concentrated on MOSFET design and assumes that thermal failure will always occur
within a protection device and that dielectric failure is prevented by keeping the voltage at
the I/Os of the intrinsic IC below a certain threshold. Only layout parameters will be varied
in the optimization process because an ESD designer usually must work within a given
process with fixed junction depths, oxide thicknesses, and doping levels. The methodology
described below was implemented in an Advanced Micro Devices 0.5µm technology.
The multifinger structure of Fig. 2.19 has three drain fingers coming off of the input pad
and four source fingers connected to VSS , yet there are six parallel NMOS transistors
because there are six poly gate fingers and each input finger serves as the drain for two
devices. A representation of a multifinger input-protection circuit is shown in Fig. 2.20.
All NMOS structures are identical, as are all the PMOS structures. Since interaction
between devices affects the overall response to an ESD input, it is simpler to analyze a
single device at a time while taking into consideration how it will perform once it is placed
in the entire circuit. Thus the design process begins with the layout of NMOS and PMOS
“single-finger” structures (individual devices) with varying layout dimensions, including