characterization, modeling, and design of esd protection circuits

146 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
constant of tc = 0.24ns is much less than the ~100ns stress time of the TLP and HBM
testing, so the constant-energy-to-failure assumption is clearly invalid.
The model further predicts that the width-normalized power to failure (Pf / a) is inversely
proportional to the square root of the pulse duration for times between tc and tb (Eq. (2.7))
and inversely proportional to the log of the pulse duration for tb < t < ta (Eq. (2.8)). For
stress times greater than ta , Pf approaches a constant value (Eq. (2.9)). Given our
technology dimensions, power to failure for the TLP and HBM stressing is expected to be
described by the inverse logarithmic dependence of Eq. (2.8).
This model focuses on power to failure rather than current to failure (If ), which is the
actual parameter of interest. However, these are related by
If =
Pf ⁄ RDUT . (5.47)
From Eqs. (2.8) and (5.47), the TLP withstand current should be inversely proportional to
the square root of the logarithm of the stress time in the time range of interest. While a
150ns transmission-line pulse of height 707mA delivers the same energy as a 75ns pulse
of height 1A (a difference in current of 29%), Eqs. (2.8) and (5.47) predict that the current
to failure is only 6% lower for the 150ns pulse than for the 75ns pulse. Therefore, while
the TLP pulse width is important, the withstand current is not critically dependent on the
pulse width over a difference range of 50%.
Although the HBM stress is not a constant-current pulse, we can assume that the thermalbox
model describes the first-order dependence between transistor dimensions and peak
current in a damage-inducing HBM pulse. By comparing VHBM,ws /1500Ω with ITLP,ws for
various TLP widths for a set of test structures, a TLP width which best correlates ITLP,ws to VHBM,ws can be determined. Fig. 5.56 plots VHBM,ws /1500Ω and ITLP,ws for 75, 100,
and 150ns pulse widths vs. DGS (2.2µm SGS) for 50/0.6µm single-finger NMOS
structures in the AMD 0.35µm CMOS process. The withstand level increases with DGS
since there is more area for dissipation of heat, but there are diminishing returns for DGS
above about 6µm. Note that the withstand levels are average values of a number of
experiments and are normalized by the total structure width (finger width times the
number of fingers), yielding units of mA/µm. Error bars represent the 95% confidence
interval of a set of measurements as calculated by the student-t distribution. In Fig. 5.57,