characterization, modeling, and design of esd protection circuits

3.1. Lattice Temperature and Temperature-Dependent Models 63
where E is the electric field, T is the lattice temperature, and τ is the energy relaxation time
of electrons in silicon and is assumed to be 0.3ps. From Eq. (3.32), the average electron
temperature in the high-field region is approximately 5300K which, using Eq. (3.30),
yields a κe of 5.4X10-4W/cm-K. By contrast, the silicon lattice has a thermal conductivity
of 0.31W/cm-K at 1000K [29]. While the thermal conductivity of the lattice is almost
1000 times greater than that of the electrons, the ratio of lattice to carrier heat diffusion is
less than 1000 because the electron temperature gradient is greater than the lattice
temperature gradient. The extent of the high-field region is about 0.2µm in the lateral
dimension (the direction of current flow, parallel to the silicon surface), and in the center
of the region the peak temperature is 1688K for the lattice and, again using Eq. (3.32),
about 5950K for the electrons. Assuming the lattice and electron temperatures are 300K at
the boundaries of the high-field region, i.e., assuming maximum thermal gradients, the
thermal flux in the lateral dimension is 4.3X10 7 W/cm 2 for the lattice and 3.0X10 5 W/cm 2
for the electrons. Therefore, the contribution of heat flux due to carrier diffusion is less
than 1% of the total flux.
Heat flux due to electron current must be calculated from the current density in the drain
junction. When the lattice temperature reaches 1688K the drain current is about 10mA per
µm of device width, of which 60% conducts laterally toward the source and 40% conducts
vertically to the substrate. The lateral current conducts uniformly through the high-field
region, which has a depth of 0.2µm as determined by the depth of the LDD junction, and
thus the current density in the high-field region is 3X10 6 A/cm 2 . Using Eq. (3.31) with the
average electron temperature of 5300K, the resulting heat flux due to current conduction is
2.0X10 6 W/cm 2 , or about 5% of the value of the lattice contribution.
From this analysis we conclude that assuming thermal equilibrium between lattice and
carriers leads to an approximately 6% underestimation of thermal dissipation away from
the region of heating. One implication of the reduced heat flux is a higher peak lattice
temperature in the device at any given time in a simulation, which may be interpreted as a
lower failure threshold for the device (simulation of thermal failure is discussed in
Section 3.6). However, in light of other uncertainties of simulation discussed in Chapters 3
and 4, a 6% error is reasonably good and thus the assumption of thermal equilibrium
between lattice and carriers is valid under most conditions. Electric fields, currents, and
carrier concentrations can be monitored during any simulation to quantify the error of the
assumption.