characterization, modeling, and design of esd protection circuits

76 Chapter 3. Simulation: Methods and Applications
(a)
I device / amps
(b)
10 0
10 -2
10 -4
10 -6
10 -8
10 -10
10 -12
10 0
10 -2
10 -4
10 -6
10 -8
10 -10
10 -12
+
V in
-
50Ω
500Ω
50Ω
V dev
DUT
0 2 4 6 8 10
V device / volts
Fig. 3.29 I-V curves for curve-tracing (solid line) and TLP (points) simulations for
a 20/0.5µm MOSFET with (a) a 2000Ω gate resistor and (b) an 8000Ω
gate resistor, with the TLP circuit shown inset. Each point represents one
non-catastrophic (maximum temperature < 1688K) 100ns TLP
simulation with a unique pulse height. The 2000Ω TLP results are
virtually identical to the curve-tracing results while the 8000Ω results are
markedly different. In the 8000Ω TLP simulations the device current
jumps from 1nA to 7mA with only a 0.06V increment in the pulse height.
I dev