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characterization, modeling, and design of esd protection circuits

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1.2. Characterizing ESD in Integrated Circuits 5<br />

<strong>characterization</strong> tests [58]. Specific tests are <strong>design</strong>ed to model specific events such as<br />

human h<strong>and</strong>ling, machine h<strong>and</strong>ling, or field induction.<br />

The most common industrial tests used to measure ESD robustness are the human-body<br />

model (HBM), the machine model (MM), <strong>and</strong> the charged-device model (CDM) [17,34].<br />

These models will be described in detail in Chapter 2. Briefly, the human-body model,<br />

also known as the finger model, consists <strong>of</strong> charging a capacitor to a high voltage (say,<br />

2000V) <strong>and</strong> then discharging the capacitor through a series resistor into an I/O or supply<br />

pin <strong>of</strong> a packaged IC with another pin grounded <strong>and</strong> all other pins floating. The capacitor<br />

<strong>and</strong> resistor values are selected to generate a pulse similar to that generated by an<br />

electrostatically charged human touching the pins <strong>of</strong> an IC, with a rise time <strong>of</strong> a few<br />

nanoseconds <strong>and</strong> a decay time <strong>of</strong> about 150ns. After an HBM stress is applied between<br />

two pins, the pins are biased at the operating voltage <strong>and</strong> the consequent leakage current is<br />

measured. If the leakage is greater than some predefined level (say, 1µA) then the package<br />

has failed the (2000V) HBM test. HBM testing is <strong>of</strong>ten the sole means <strong>of</strong> qualifying ESD<br />

reliability because the specifications <strong>of</strong> the test are st<strong>and</strong>ardized industry wide <strong>and</strong> because<br />

several commercial HBM testers are available.<br />

As in the HBM, in the machine model a capacitor is charged up to a high voltage <strong>and</strong> then<br />

discharged through the pins <strong>of</strong> an IC. Unlike the HBM, however, the MM discharges the<br />

capacitor through only a very small, parasitic series resistance, resulting in an oscillatory<br />

input pulse comparable to a pulse generated by a charged metal machine part contacting<br />

an IC pin. Since the series resistance is very small, parasitic inductances <strong>and</strong> capacitances<br />

<strong>of</strong> the tester as well as the dynamic impedance <strong>of</strong> the device under test have a much larger<br />

effect on the shape <strong>of</strong> the pulse, making a st<strong>and</strong>ard, repeatable MM test difficult to<br />

actualize.<br />

While device heating is the primary failure mechanism in the HBM <strong>and</strong> MM, dielectric<br />

failure is the signature <strong>of</strong> the charged-device model. Due to the sub-nanosecond rise time<br />

<strong>of</strong> the CDM pulse, <strong>protection</strong> devices may not be able to turn on <strong>and</strong> clamp the input<br />

voltage to a safe level before high-field oxide damage occurs. The CDM test, which<br />

consists <strong>of</strong> charging a substrate (ground) pin <strong>of</strong> a package using a voltage source,<br />

removing the voltage source, <strong>and</strong> then discharging the package by shorting a different pin,<br />

is meant to simulate the electrostatic charging <strong>of</strong> a package due to improper grounding <strong>and</strong><br />

the subsequent discharging when a low-resistance path becomes available. Though much

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