characterization, modeling, and design of esd protection circuits

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192 Appendix A. Tracer User’s Manual Other information regarding the trace must be inferred from the PISCES output displayed while Tracer is running (not shown). From this output we can see that voltage biasing was used on the open base contact for the first few solutions, in which the collector current is too small to allow stable use of zero-current biasing. A few PISCES simulations are actually run for each I-V point, with minor adjustments on the base voltage being made until the base current is less than ABSMAX. When the collector current is large enough, Tracer places a zero-current bias on the base. We can also see that a variable load resistor is placed on the collector when the collector current exceeds MINCUR. After this, the step sizes are regulated to produce a smooth curve. A.9.2 GaAs MESFET In this example, the drain of a GaAs MESFET is biased with respect to the grounded source with the gate set at -0.5V and the substrate grounded. Before Tracer can be used to sweep the drain electrode, a solution must be created, using PISCES-2ET, to set up the gate bias. The input deck shown in Fig. A.67 and Fig. A.68 defines the device, finds the thermal-equilibrium solution, and then steps the gate bias to -0.5V while holding the other electrodes at 0V. The mesh and solution files are saved to the files mes.mesh and mesvg.5.ini, respectively. For Tracer, another PISCES input deck must be created to use as the input file (Fig. A.69). In mesvg.5.pis the mesh file generated by mes.pis, mes.mesh, is read in, preempting the mesh, eliminate, region, electrode, and doping cards. Since Tracer will be starting with a previous solution, the name of the solution file to load must be given in mesvg.5.pis. This load statement appears directly above the solve card with the file name mesvg.5.ini, the solution file generated by mes.pis. The trace file mesvg.5.tra is shown in Fig. A.70. In the three FIXED cards, the voltages of the source and substrate (num=1 and num=4, respectively, as defined by mes.pis) have been fixed at 0V, while the gate voltage (num=2) has been fixed at -0.5V. The current through the gate electrode will be recorded for each solution in the output file. The CONTROL card of mesvg.5.tra specifies that the drain (num=3) will be swept from 0.0V to a voltage where the current is greater than or equal to 4.1X10 -4A/µm, with an initial drain voltage step of 0.2V. On the SOLVE card, FIRSTSOLUTION is specified as LOAD, consistent with the input file mesvg.5.pis, and PISCES-2ET is designated as the
A.9. Examples 193 title mes.pis mesh nx=53 ny=41 rect diag.fli outf=mes.mesh x.m n=1 l=0 r=1 x.m n=5 l=1 r=0.85 x.m n=8 l=2 r=1.3 x.m n=11 l=3 r=0.7 x.m n=13 l=3.5 r=1 x.m n=18 l=4 r=0.8 x.m n=24 l=4.5 r=1.15 x.m n=32 l=5 r=0.85 x.m n=40 l=6 r=1.2 x.m n=43 l=7 r=1 x.m n=46 l=8 r=1.35 x.m n=49 l=9 r=0.7 x.m n=53 l=10 r=1.15 y.m n=1 l=-.01 r=1 y.m n=4 l=0.0 r=1 y.m n=7 l=0.01 r=1 y.m n=9 l=0.025 r=1 y.m n=20 l=0.19 r=1 y.m n=26 l=0.36 r=1.15 y.m n=39 l=3.0 r=1.25 y.m n=41 l=6.0 r=1.25 elim y.dir iy.lo=1 iy.hi=3 ix.lo=1 ix.hi=4 elim y.dir iy.lo=1 iy.hi=2 ix.lo=1 ix.hi=4 elim y.dir iy.lo=1 iy.hi=6 ix.lo=19 ix.hi=31 elim y.dir iy.lo=1 iy.hi=5 ix.lo=19 ix.hi=31 elim y.dir iy.lo=1 iy.hi=4 ix.lo=19 ix.hi=31 elim y.dir iy.lo=1 iy.hi=3 ix.lo=19 ix.hi=31 elim y.dir iy.lo=1 iy.hi=3 ix.lo=50 ix.hi=53 elim y.dir iy.lo=1 iy.hi=2 ix.lo=50 ix.hi=53 elim y.dir iy.lo=23 iy.hi=41 ix.lo=2 ix.hi=52 elim y.dir iy.lo=29 iy.hi=41 ix.lo=2 ix.hi=52 elim y.dir iy.lo=33 iy.hi=41 ix.lo=2 ix.hi=52 elim y.dir iy.lo=40 iy.hi=41 ix.lo=2 ix.hi=52 elim x.dir iy.lo=2 iy.hi=40 ix.lo=2 ix.hi=52 elim x.dir iy.lo=2 iy.hi=40 ix.lo=2 ix.hi=52 elim y.dir iy.lo=2 iy.hi=40 ix.lo=2 ix.hi=52 elim x.dir iy.lo=2 iy.hi=40 ix.lo=2 ix.hi=52 elim y.dir iy.lo=2 iy.hi=40 ix.lo=2 ix.hi=52 Fig. A.67 The mesh generation and eliminate statements of the file mes.pis for the GaAs MESFET example.
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
Page 177 and 178: 5.4. Optimization 161 Qualitatively
Page 179 and 180: 5.5. Summary of Design Methodology
Page 181 and 182: Chapter 6 Conclusion In the integra
Page 183 and 184: 6.1. Contributions 167 TLP was show
Page 185 and 186: 6.2. Future Work 169 most ESD quali
Page 187 and 188: 6.2. Future Work 171 Significant wo
Page 189 and 190: Appendix A Tracer User’s Manual S
Page 191 and 192: A.3. CONTROL Card 175 A.3 CONTROL C
Page 193 and 194: A.4. FIXED Card 177 A.4 FIXED Card
Page 195 and 196: A.5. OPTION Card 179 • DAMP is a
Page 197 and 198: A.5. OPTION Card 181 A.5.4 Examples
Page 199 and 200: A.6. SOLVE Card 183 if the voltage
Page 201 and 202: A.7. Input Deck Specifications 185
Page 203 and 204: A.9. Examples 187 column contains c
Page 205 and 206: A.9. Examples 189 fixed num = 1 typ
Page 207: A.9. Examples 191 Collector Current
Page 211 and 212: A.9. Examples 195 simulator to use.
Page 213 and 214: A.9. Examples 197 #Soln #Vctrl Ictr
Page 215 and 216: Bibliography [1] T.J. Green and W.K
Page 217 and 218: Bibliography 201 [20] C. Duvvury, R
Page 219 and 220: Bibliography 203 [42] S.M. Sze, Phy
Page 221 and 222: Bibliography 205 [63] R. van Overst
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