characterization, modeling, and design of esd protection circuits

5.2. Application 155
To determine how to best describe the layout dependence of the withstand current and
voltage using a second-order linear model, single-factor trends are examined for DGS,
SGS, n, and W. In Fig. 5.56, the normalized VHBM,ws vs. DGS line has a negative
curvature, indicating that the ITLP,ws and VHBM,ws model equations should have quadratic
as well as linear DGS terms, with the quadratic terms being negative. A quadratic
dependence on SGS is also observed, but over the limited range of the design space (2.2 to
4.2µm) a linear term is adequate. As seen in Fig. 5.57, the normalized failure parameters
have an inverse dependence on the number of fingers, and consequently these parameters
are not well described using linear and quadratic n (number-of-finger) factors. However, if
1/n is chosen as the factor, a good fit is obtained with just a linear term. Since the
normalized ITLP,ws and VHBM,ws also have an inverse dependence on width, 1/W is
chosen as a factor, but in this case the best fit is obtained by also including a quadratic
term. Finally, we assume that SGS does not interact with any of the factors since its value
does not vary widely, but the three interaction terms between DGS, 1/n, and 1/W are
included. The resulting withstand-current model is
ITLP, ws
----------------- = c
( Wn)
0 c1( SGS)
c2 ( DGS)
c3 ( DGS)
2
+ + + + c4 ( 1⁄ n)
+ c5 ( 1 ⁄ W)
c6 ( 1 ⁄ W)
2
+ + c7 ( DGS)
( 1 ⁄ n)
+ c8 ( DGS)
( 1 ⁄ W)
+ c9 ( 1 ⁄ n)
( 1 ⁄ W)
(5.53)
with an identical equation (with different coefficient values) for VHBM,ws . Note that the
constant coefficient, c0 , lumps together the constant terms from the separate factor
dependencies.
Model coefficients for Eqs. (5.51)-(5.53) were extracted using Catalyst for two
development lots with slightly different process recipes. HBM and 150ns TLP
characterization of the design space was performed on two wafers per lot and five die sites
per wafer, with average response values of each structure used as the Catalyst input.
SRAM test circuits from the same wafers were submitted to the AMD Reliability
Laboratory for HBM stressing of I/O vs. VSS , I/O vs. VCC , and VCC vs. VSS pin
combinations to determine average, i.e., not qualification, HBM withstand voltages.
Results for the two lots are summarized in Table 5.2. For each lot, the layout parameters of
each stressed circuit were plugged into the ITLP,ws model equation to determine the
mA ⁄
µm values in Table 5.2. These values were then converted to VHBM,ws values by