characterization, modeling, and design of esd protection circuits

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100 Chapter 4. Simulation: Calibration and Results I d (a) (c) I d V gs V ds -V bs (b) (d) V gs log(I d ) (e) log(I d ) V gs log(I b ) Fig. 4.40 Qualitative depiction of I-V curves used for MOSFET calibration: (a) drain: I d vs. V ds for stepped V gs ; (b) gate: I d vs. V gs for stepped V bs ; (c) subthreshold: log(I d ) vs. V gs for stepped V ds ; (d) substrate: log(I b ) vs. V gs for stepped V ds ; (e) breakdown: log(I d ) vs. V ds for stepped V gs . The subscripts d, s, g, and b refer to the drain, source, gate, and substrate, respectively. Ideally, model coefficients should also be calibrated over a high-temperature range because there is heating during an ESD event which affects the semiconductor properties (refer to Eqs. (3.22), (3.23), (3.25), and (3.29)). For example, at increased temperatures the mobility and II-generation rate degrade due to increased scattering, thereby reducing the saturation drain current of Fig. 4.40a and increasing the breakdown voltage of Fig. V ds V ds V gs V gs V ds
4.1. Calibration Procedure 101 4.40e. Wafer-level I-V data can be taken at temperatures up to around 500K using a hot chuck and then used as a basis for calibrating model coefficients in high-temperature simulations. For calibration of this AMD technology, however, it is assumed that the temperature dependences in the mobility and II models, which are qualitatively correct and have been fit to high-temperature data of other technologies [47,49], are accurate enough using default coefficient values. The benefit of high-temperature calibration is actually limited because for sub-microsecond ESD events the high-temperature region is localized--perhaps covering as little as 10 percent of the simulation space--and thus the temperature dependence of the mobility and II models may not have much effect on the overall I-V curve. Also, these models have only been shown to be valid up to a certain temperature, e.g., 460K for mobility [47], close to the limit of hot-chuck measurements, but critical ESD effects occur at higher temperatures. And even if the mobility and II models are calibrated at high temperatures, other simulation models are suspect. For example, at 900K the band-gap shrinkage model predicts a band gap energy about 40mV higher than the measured value [60]. Instead of calibrating mobility and II coefficients at high temperatures to fit ESD thermal-failure simulations, the approach taken here is to adjust the thermal boundary conditions, i.e., the placement of the thermal contacts and use of lumped thermal resistors and capacitors, to match simulated and experimental data. Since the true thermal boundary conditions are not known exactly, adjusting the thermal contacts and lumped elements to fit simulated thermal failure to ESD data is a reasonable way to determine their values. Discussion of the calibration of thermal effects is not taken up until Section 4.1.4. For all of the MOSFET simulations described in this subsection, the initial lattice temperature is set to 297K and is allowed to increase in regions of heat generation (Eq. (3.15)) as determined by the thermal diffusion equation (Eq. (2.2)). Constant-temperature boundary conditions are placed on the bottom and sides of the simulation structures as a simple way of modeling the large heat sink of the bulk silicon, but these are not really important because the maximum temperature during any of the MOSFET simulations is less than 310K. Calibration of the Lombardi mobility model began with simulations of the gate characteristic shown in Fig. 4.40b. To reduce simulation time, a one-carrier (electron) solution method was used because hole current is negligible in an NMOS transistor in its normal operating range. This implies that only the electron mobility coefficients are adjusted during calibration. Initial simulations of the 0.5µm and 3.0µm structures using default values
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113 and 114: 4.1. Calibration Procedure 97 and t
Page 115: 4.1. Calibration Procedure 99 conta
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125 and 126: 4.1. Calibration Procedure 109 simu
Page 127 and 128: 4.1. Calibration Procedure 111 (a)
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133 and 134: 4.1. Calibration Procedure 117 simu
Page 135 and 136: 4.1. Calibration Procedure 119 volt
Page 137 and 138: 4.2. MOSFET Snapback I-V Results 12
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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