characterization, modeling, and design of esd protection circuits

5.1. Methodology 147
the same withstand currents are plotted vs. the number of 50/0.6µm fingers (4.4µm DGS,
2.2µm SGS) for various multiple-finger NMOS transistors. In this case the normalized
withstand level decreases as the number of fingers increases. The flow of heat away from a
finger is reduced by heating in adjacent fingers due to the reduced temperature gradient,
thus leading to thermal runaway at a lower normalized current level for a multiple-finger
circuit.
As seen in Fig. 5.56 and Fig. 5.57, for the standard single-finger structure (50/0.6µm with
4.4µm DGS), shorter TLP pulse widths lead to higher withstand currents, with a range
greater than 30%. However, for larger DGS and for the multiple-finger structures, this
difference decreases and in many cases the difference is less than the range of the error
bars. In both figures the HBM results are seen to follow the same trend as the TLP results,
but there is no TLP width for which correlation of ITLP,ws to VHBM,ws is clearly superior.
This is somewhat expected since the theoretical difference in withstand currents of 6% is
mA / µm
40
30
20
10
4 5 6
DGS / µm
7 8
150ns TLP 100ns TLP 75ns TLP HBM/1.5
Fig. 5.56 Normalized (divided by width) withstand current vs. drain-side CGS for
HBM stressing and 75, 100, and 150ns TLP stressing of 50/0.6µm singlefinger
transistors. For HBM, the withstand voltage is converted to mA by
dividing by 1.5. Error bars represent 95% confidence intervals.