characterization, modeling, and design of esd protection circuits

6.1. Contributions 167
TLP was shown to be a powerful tool for extracting the critical I-V parameters of ESD test
structures fabricated in a leading-edge CMOS technology. A discussion was given on the
dependence of these critical I-V parameters on process and layout parameters. Testing
focused on structures with varying widths and contact-to-gate spacings, and power to
failure and current to failure were measured between 50ns and 600ns. The usefulness of
the extracted I-V parameters and failure levels was demonstrated in the application of the
ESD design methodology to SRAM circuits.
6.1.2 Numerical Device Simulation
Lattice-temperature modeling in 2D numerical device simulation and the temperaturedependent
models required for proper modeling of high-temperature effects associated
with ESD were reviewed. New simulation methods were presented, including a generalpurpose
curve-tracing algorithm, developed and implemented as a C program, which
guides a simulator through complex I-V curves. The curve tracer’s application to ESD was
demonstrated in the control of dc snapback simulations. More general applications of the
curve tracer and a user’s manual are presented as an appendix. A quantitative analysis was
conducted to compare and contrast the 2D and 3D formulations of an analytic thermal
model which, to first order, describes the heating of a device during an ESD event. The
results of the analysis predict that for stress times in the ESD and EOS regimes, the power
to failure modeled in two dimensions will be higher than that of the three-dimensional
model or of an actual device. This directly conflicts the conclusions reached in previous
studies of electrothermal simulation that 2D simulations underestimate the power to
failure. Methods for studying dielectric failure and latent damage with 2D simulation were
proposed, including monitoring of hot-carrier injection and hot-spot spreading during an
ESD simulation.
A procedure for calibrating simulation models for use in quantitative ESD simulations
was delineated, including structure definition and determination of mobility and impactionization
model coefficients and thermal boundary conditions. I-V and failure
characteristics of standard test structures were used as the basis of the calibration. While
quantitative modeling of the snapback I-V parameters was achieved, modeling of thermal
failure was inadequate due to unresolved issues regarding modeling of the electric field at
high current levels in the drain junction region, where the device physics are most critical
and most complex. Usefulness of the ESD snapback simulations was nonetheless