characterization, modeling, and design of esd protection circuits

2.2. Transmission Line Pulsing 25
In the simplest theory, thermal runaway and device failure follow instantaneously when
the intrinsic carrier concentration exceeds the background doping concentration at a
certain point in the device [12]. However, this model is too simple because it does not
account for spreading resistance and the temperature dependence of mobility and impactionization
rates. Although the resistivity at the hot spot decreases, the surrounding hightemperature
region still has a high resistivity, and the overall device resistance may not
decrease until there is a large area in which the intrinsic concentration is larger than the
doping. For a very short pulse duration, the temperature at the hot spot may exceed the
melting point and create damage without the device entering second breakdown. As
mentioned in Chapter 1, even when the current density is high enough to trigger thermal
runaway and the device voltage drops, for a narrow-width structure there may not be
enough total current to cause major damage, i.e., leakage current greater than 1µA or a
short or open circuit. Therefore, second breakdown refers to a drop in device voltage due
to the negative differential resistance resulting from device heating and is not synonymous
with device failure.
There is one other phenomenon which may occur in LDD MOS protection devices which
has received little or no attention. It has been reported that in bipolar technologies making
use of an epitaxial layer to form a lightly doped collector region (an n-p-n-n + transistor),
two non-thermally induced snapbacks may occur during a BVCEO stress [37]. The first
snapback is due to the same mechanism described above in which II-generated holes
forward bias the base-emitter junction. Beyond the snapback point the current steeply
rises, but β goes through a maximum and then falls off rapidly due to the effects of highlevel
injection (base pushout). Since the gain is decreasing, the level of current must be
maintained by increasing the collector voltage (Vce ), which increases the II generation by
expanding the width of the high-field region further into the epi layer. In this area of
operation the I-V curve flattens out due to the additional voltage needed. If the epi layer is
thin enough, the peak electric field will move from the lightly doped epi into the heavily
doped substrate as Vce continues to increase. Due to the higher doping level the electric
field profile becomes higher and narrower. Additionally, high-level injection has made a
large part of the epi layer charge neutral, and thus a voltage cannot be sustained across this
region. The net result is a drop in Vce , i.e., a second snapback. This phenomenon was
predicted with PISCES simulations and was tenably verified by experiments as reported in
[37]. In an ESD protection MOSFET, the drain LDD region acts like a lightly doped epi