characterization, modeling, and design of esd protection circuits

6.2. Future Work 171
Significant work has already been done to create compact models for MOSFET snapback
and thermal failure [73-75]. Although thermal modeling is best implemented by
enhancing the source code of a circuit simulator, parasitic bipolar action, i.e., snapback,
can be modeled by adding existing lumped-element bipolar transistor and current
generator models in a simulator such as HSPICE. Such modeling is probably adequate for
the study of charged-device model stressing: CDM failures are usually dielectric rather
than thermal in nature, so failure can be studied by monitoring the voltage across the gate
oxides in the simulated circuit.
6.2.3 Design
One obvious way to improve the ESD circuit design methodology presented in Chapter 5
is to increase the range and number of variables in the design space. For the next AMD
technology, 0.25µm CMOS, a more complete ESD transistor design space has already
been laid out, with gate length included as one of the variables. Gate length is a factor to
which CDM robustness may be especially sensitive. One of the shortcomings of the
current implementation of the methodology is that the design space is not optimized and
not all corners of the space are covered, resulting in nonphysical values of withstand
current for the combination of large drain-to-gate spacing and large width. For the 0.25µm
technology the design space has been laid out with model extraction in mind by using the
Catalyst software’s design-of-experiment capability.
Currently, the methodology is undergoing further verification by applying the modeling to
protection circuits of other AMD CMOS logic products in the 0.35µm technology. One
important product category is RF (high frequency) circuitry, in which I/O capacitance
must be kept to a relatively low value in order to meet operating specifications. As
demonstrated in Section 5.4, the design methodology allows for optimization under the
constraint of a maximum allowable transistor area, i.e., maximum allowable capacitance.
Additionally, the I/O gate delay of an RF circuit must not be too large. This translates to a
constraint on maximum width of the poly gate fingers, which again can be accounted for
during design optimization.
Future plans include expanding the methodology to study special I/O circuits such as
those used in ICs with separate internal and external power supplies and in ICs which are
“5-volt tolerant.” In the former case, the substrate of an I/O pull-down transistor is tied to