characterization, modeling, and design of esd protection circuits

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110 Chapter 4. Simulation: Calibration and Results and does not diminish the value of the simulation because the results of interest all occur at current levels above 100µA. The thermal boundary conditions consisted of overlapping the electrical contacts with constant-temperature (297K) thermal contacts with no thermal resistance. Although the simulations examined here are referred to as calibration simulations, if the mobility and impact-ionization models have already been fixed by the MOSFET-characteristic calibration, then comparing the measured and simulated Vt1 , Vsb , and Rsb is really a verification procedure rather than a calibration procedure. An example of the I-V curve of a dc snapback simulation is shown in Fig. 4.42. The horizontal line in the log curve shows where the solutions began incorporating the thermal-diffusion equation. Note that although the lattice temperature does not significantly increase above 300K until after snapback, the breakdown voltage is substantially lower without including the thermal diffusion equation because the temperature-dependent impact-ionization model cannot be used. Two things were immediately noticeable from the initial snapback simulations. First, the snapback resistance appeared to be a reasonable value (compared to experiment) immediately after snapback, but the curve quickly rolled over at higher currents, indicating a much higher resistance than in the experimental structures. Second, even when the snapback voltage was extrapolated from the initial, steep part of the snapback portion of the curve, i.e., using a value of Rsb equal to the measured value, the snapback voltage was about 1.8V too high. It was apparent from these simulations that calibration of the mobility and impactionization models using the standard MOSFET curves was inadequate for snapback simulations and thus that further manipulation of the model coefficients was needed. Since the problem regarding the high snapback voltage was the simplest to understand, it was dealt with first. The high Vsb value indicates that the impact-ionization generation rate is too low for a given electric field in the snapback region of the I-V curve because the simulated voltage (and electric field) needed to sustain a given current level is too high. As shown by Eq. (3.27) and Fig. 3.22, the impact-ionization rate for electrons is determined ∞ crit by two model coefficients, αn and En (or λn , which by Eq. (3.28) is inversely crit proportional to En ), assuming βn is constant. In the calibration of the MOSFET ∞ substrate characteristic, αn was held constant and λn was varied until the effective II rate resulted in the proper amount of substrate current. A good fit of the substrate characteristic was attained because, as Fig. 3.22 shows, if the spread in peak electric field values throughout the stress conditions of the substrate-current test is relatively narrow, the
4.1. Calibration Procedure 111 (a) (b) log(I device (A/µm)) I device (mA/µm) -2 -3 -4 -5 -6 4 3 2 1 + Vdevice - I device 1/R sb (measured) 0 0 2 4 6 8 Vsb 10 12 14 V device / volts V t1 Fig. 4.42 Device current per width is plotted on a log (a) and linear (b) scale vs. device voltage for a dc-sweep simulation of the standard structure with proper gridding and impact-ionization modeling. The snapback voltage is extracted using a line determined by the measured snapback resistance. To compare the linear curve to Fig. 4.41, multiply the current per width by 50µm.
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113 and 114: 4.1. Calibration Procedure 97 and t
Page 115 and 116: 4.1. Calibration Procedure 99 conta
Page 117 and 118: 4.1. Calibration Procedure 101 4.40
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125: 4.1. Calibration Procedure 109 simu
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133 and 134: 4.1. Calibration Procedure 117 simu
Page 135 and 136: 4.1. Calibration Procedure 119 volt
Page 137 and 138: 4.2. MOSFET Snapback I-V Results 12
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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