characterization, modeling, and design of esd protection circuits

Chapter 1
Introduction
Electrostatic discharge (ESD) is one of the most important reliability problems in the
integrated circuit (IC) industry. Typically, one-third to one-half of all field failures
(customer returns) are due to ESD and other failures known collectively as electrical
overstress (EOS) [1-3]. As ESD damage has become more prevalent in newer
technologies due to the higher susceptibility of smaller circuit components, there has been
a corresponding increase in efforts to understand ESD failures through modeling and
failure analysis. This has resulted in a greater industry-wide knowledge of ESD
mechanisms and thus a greater ability to design robust ICs which sustain fewer field
failures. Despite these efforts, there are still ESD-related problems which are not well
understood, especially the phenomenon of “latent damage.”
There are two ways to reduce IC failures due to ESD. One is to ensure proper handling
and grounding of personnel and equipment during manufacturing and usage of packaged
chips, i.e., to prevent ESD events from occurring. The other approach is to connect
protection circuits (almost always on-chip) to the pins of a packaged IC which will divert
high currents away from the internal circuitry and clamp high voltages during an ESD
stress. A chip manufacturer has limited control over a customer’s handling of its product,
so incorporating effective protection circuitry is essential. Since the spectrum of stresses
under the label of EOS/ESD is broad and the amplitude of stress is virtually unlimited, it is
not possible to guarantee total EOS/ESD immunity. However, through the proper design
of protection circuitry the threshold of sustainable stress can be significantly increased,
resulting in improved reliability of ICs.
Designing ESD protection circuits becomes more challenging as device dimensions
shrink, particularly in MOS technologies [40,57]. As ICs become smaller and faster,
susceptibility of the protection circuits to damage increases due to higher current densities
1