characterization, modeling, and design of esd protection circuits

156 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
Table 5.2 Experimental and modeled SRAM HBM withstand voltages.
Pin Combination
multiplying by the total circuit width and by 1500Ω. The different stress combinations and
the model predictions and the SRAM testing, with the exception of I/O vs. VCC testing of
the corresponding protection circuits involved will be discussed in the next section, as will
the generally slightly higher withstand levels seen in Lot 2 for SRAM HBM testing and
for TLP characterization throughout the design space. Good agreement is seen between
Lot 2 and VCC vs. VSS testing of both lots. These discrepancies will also be discussed in
the next section.
5.3 Analysis
5.3.1 Model Terms
Full I/O vs.
V SS
Input vs.
V SS
I/O vs.
V CC
V CC vs.
V SS
Circuit Stressed 1/2 Pull Down Pull Down Clamp Clamp
W X n (µm) 36.2 X 5 36.2 X 10 71 X 5 71 X 5
DGS/SGS (µm) 4.2/2.2 4.2/2.2 4.2/4.2 4.2/4.2
Lot 1
model mA/µm
model VHBM,ws exptl. VHBM,ws Lot 2
model mA/µm
model VHBM,ws exptl. VHBM,ws 19.0
5200
5200
19.1
5200
5400
13.9
7550
7500
15.1
8200
8000
10.4
5500
5400
13.7
7300
4600
10.4
5500
>10,00
13.7
7300
>10,00
Before further discussion of the SRAM predictive modeling, we will examine the Catalyst
model terms in more detail. Fig. 5.60 is the model-graph window generated by Catalyst
for Lot 1, which graphically displays the dependence of each response on the four layout
factors. Qualitatively similar trends are seen for Lot 2. As a factor changes from its low
value to its high value, it affects each response as indicated by the corresponding trend
line. In all graphs the error bars reflect typical experimental variations of the responses as
determined from the input data. Notice that for Vsb and ⋅
( Wn)
the 1/n and 1/W lines
R sb