characterization, modeling, and design of esd protection circuits

Chapter 5
Design and Optimization of ESD
Protection Transistor Layout
To ensure electrostatic discharge (ESD) robustness, a chip designer must follow certain
guidelines concerning size and placement of diode and transistor clamps between different
power-supply buses as well as between I/Os and supply lines. These guidelines may
typically be provided by technology design rules which include minimum transistor
width, optimal contact-to-gate spacing (CGS), and examples for placement and hook-up
of the various protection circuits. If all of the ESD design rules are followed, the circuit
designer presumes that some minimal ESD requirement will be met, typically a humanbody
model (HBM) withstand voltage of 2000V. However, until actual silicon is packaged
and tested, the designer usually does not know what HBM voltage the product will
withstand or what quantitative changes must be made in protection-circuit layout
parameters to reach a certain level of ESD robustness. The aim of this chapter is to
provide circuit designers with a methodology enabling the design of ESD circuitry which
meets a product’s specific reliability needs. Provided a quantitative model, or layout rules
based on this model, a circuit designer can create the optimal design for a given area and
have a good idea of how robust the design will be.
As discussed in Chapter 2, numerous papers have analyzed the effectiveness of
transmission-line pulsing (TLP) measurements in characterizing the ESD response of
CMOS processes and circuits [21,23]. The dependence of MOS snapback I-V
characteristics on layout parameters, addressed in Section 2.4, is well known [8]. While
layout optimization for ESD circuits has been investigated [65,66], only recently has work
been presented on a methodology which uses TLP measurements to quantitatively predict
the HBM withstand voltage of any protection transistor for a given technology or to
139