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characterization, modeling, and design of esd protection circuits

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5.1. Methodology 145<br />

reaches its peak. This is justified because less than 4% <strong>of</strong> the pulse energy is contained in<br />

the time before the pulse reaches its peak value. Substituting Eq. (5.44) into Eq. (5.42),<br />

HBM<br />

Efail Ipk<br />

2 RHBMCHBM = RDUT---------------------------- . (5.45)<br />

2<br />

Equating Eq. (5.45) to Eq. (5.43), we see that for equivalent energies the TLP pulse width<br />

must be 75ns for the same peak current (ITLP = Ipk = VHBM /RHBM ).<br />

To determine the validity <strong>of</strong> the assumed adiabatic boundary conditions, we need to<br />

reexamine the three-dimensional thermal-failure model presented in Section 2.2.2. Recall<br />

that in this “thermal-box” model for an MOS transistor a uniform Joule heating due to a<br />

constant-current stress is assumed to occur in a rectangular parallelepiped whose<br />

dimensions are defined by the transistor width, the drain junction depth, <strong>and</strong>, roughly, the<br />

gate length. Failure is assumed to occur when the peak temperature at the center <strong>of</strong> the box<br />

reaches a critical value. The ballast resistances <strong>of</strong> the non-silicided source <strong>and</strong> drain<br />

regions create additional potential drops <strong>and</strong> heat sources which affect the boundary<br />

conditions. Nonetheless, we still expect the model to serve as a first-order description <strong>of</strong><br />

device failure.<br />

Using this model the power to failure (Pf ) is calculated vs. stress time (tf ), with four<br />

regions <strong>of</strong> the Pf vs. tf curve bounded by three time constants which are determined by the<br />

box dimensions (Fig. 2.12). Each time constant is defined as<br />

t i<br />

=<br />

i 2<br />

⁄<br />

( 4πD)<br />

(5.46)<br />

where D is the thermal diffusivity <strong>and</strong> i takes on specific values <strong>of</strong> a, b, or c, which for our<br />

technology are assumed to be 50µm for the transistor width (a), 0.5µm for the gate length<br />

(b), <strong>and</strong> 0.2µm for the junction depth (c). Using D = 0.13cm 2 /s (based on the calculations<br />

from [23]), these result in values <strong>of</strong> ta = 15µs, tb = 1.5ns, <strong>and</strong> tc = 0.24ns.<br />

The model allows us to determine that the power to failure, normalized by the transistor<br />

width (Pf / a), is inversely proportional to stress time for times less than tc (Eq. (2.6)).<br />

Since the product <strong>of</strong> the power to failure <strong>and</strong> the time to failure is constant in this region, a<br />

constant energy is needed to induce failure, i.e., this is the adiabatic region. The time

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