characterization, modeling, and design of esd protection circuits

3.4. Previous ESD Applications 71
value incident at the collector. A resistor, Rb , is placed between the base contact and
ground to couple the base voltage to the input voltage via the collector-base junction
capacitance. This resistor facilitates turn-on of the transistor by forward biasing the baseemitter
junction and thus is similar to the MOS gate-bounce technique depicted in Fig.
2.17a. The purpose of the simulations was to determine the effects of tr , Rb , and the device
geometry on the trigger voltage of the circuit, with a design goal of keeping Vt1 below a
critical value. They found that even when Rb is set to its upper limit (as determined by the
required switching time of the circuit), the npn will not turn on if the pulse rise time is
greater than about 10ns because the base voltage is not sufficiently biased. To solve this
problem extra coupling of the base to the input was provided by placing a MOSFET in
parallel with the BJT with the collector tied to the input, source tied to npn base, and gate
tied to ground through a large resistance (Fig. 3.28). Similar to the coupling techniques
V max
+
-
M1 M2
R b
10 15 Ω
Fig. 3.28 ESD protection circuit used for SPICE simulations by Chatterjee et al.
[33]. M1 is an NMOS transistor designed to facilitate the turn-on of the
npn transistor during ESD. M2 represents the output NMOS transistor
being protected.
described in Section 2.3, the NMOS device will turn on during an ESD pulse to form a
channel between the input and npn base to turn on the npn transistor. SPICE simulations
were used to verify the design. Since SPICE cannot model the npn breakdown, circuit
simulation is only used to determine if the base is sufficiently biased for a given layout and
input pulse. (Using contemporary simulators the entire circuit response can be modeled
with mixed-mode simulation, using PISCES to model the BJT and either PISCES or
SPICE to model the NMOS transistor.) The authors concluded that their modeling