characterization, modeling, and design of esd protection circuits

2.4. Dependence of Critical MOSFET I-V Parameters on Process and Layout 45
effects of these parameters on ESD circuit robustness. Before further discussing these
effects and defining a circuit design strategy, we will look at the dependence of Vbd , Vt1 ,
It1 , Vsb , Rsb , Vt2 , and It2 (all defined in Fig. 2.6) on several process and layout parameters.
The time to trigger, t1 , and the time to second breakdown, t2 , are also important
parameters, but they are really more a function of the incoming pulse profile. As noted
before, t1 decreases as the pulse ramp rate increases, while t2 decreases as the power in the
pulse increases. Given a fixed input pulse, a reduction in Vt1 and/or It1 implies a reduction
in t1 . The effects of process and layout parameters on the critical MOS parameters are
discussed below and summarized in Table 2.1. Note that in this discussion the snapback
voltage, Vsb , will be defined as the minimum voltage after the device is triggered rather
than the value extrapolated from the snapback region back to the x-axis as in Fig. 2.6. This
is done because the extrapolated Vsb depends not only on the minimum voltage in the
snapback region but also on the snapback resistance.
• Gate length -- Since the gate length, L, is effectively the base width of the parasitic
bipolar transistor, it has a strong effect on the I-V curve. As mentioned in Section 2.2.1,
the ratio of the breakdown voltage to the snapback voltage is β 1/n , the current gain of
the bipolar transistor raised to some power. The breakdown voltage should be determined
only by the drain-substrate junction profile and thus be constant vs. gate length,
unless the gate length is so short that punchthrough occurs before avalanche breakdown.
To first order, , so Vsb should be proportional to L 2/n β 1 L , assuming no
potential drops outside of the intrinsic device. For a typical experimental value of n =
5.5, doubling the gate length should increase Vsb by 29%. Rsb is higher for a longer
channel, but this dependence may not be detectable since the series resistance due to
the contact-to-gate spacing is usually dominant. Vt1 and It1 , and thus the turn-on time,
also increase with L because the diffusion of holes to the source which triggers snapback
becomes less efficient and more impact ionization must be provided by increased
current and electric field. Finally, It2 should increase with gate length because there is a
larger area over which heat generated in the drain depletion region can dissipate. This is
in agreement with the 3D thermal box model.
2
∝
⁄
• Gate width -- If a MOS transistor is operating uniformly over its entire width, W, then
the current parameters It1 and It2 should scale directly with device width. This means
more current is needed to turn on the device, but it also means the device should be
more robust since the width of the box in the 3D thermal model is larger. The voltage