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characterization, modeling, and design of esd protection circuits

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16 Chapter 2. ESD Circuit Characterization <strong>and</strong> Design Issues<br />

in CMOS technologies <strong>and</strong> then a discussion <strong>of</strong> critical parameters in <strong>protection</strong> <strong>circuits</strong><br />

(which can be measured with TLP) <strong>and</strong> the dependence <strong>of</strong> these parameters on layout<br />

variations. Finally, the concepts <strong>of</strong> the chapter are brought together to form an ESD<br />

<strong>protection</strong>-circuit <strong>design</strong> methodology.<br />

2.1 Classical ESD Characterization Models <strong>and</strong> Industrial Testing<br />

The most popular model used in industry to test ESD robustness is the human-body model<br />

(HBM), also known as the finger model. The st<strong>and</strong>ardization <strong>of</strong> this test, first documented<br />

in 1980 <strong>and</strong> most recently updated in 1989 as military st<strong>and</strong>ard MIL-STD 883.C/3015.7<br />

[17], is a result <strong>of</strong> extensive ESD research since the mid 1970s. In this model a 100pF<br />

capacitor is charged up to a certain voltage <strong>and</strong> then discharged through a 1500Ω resistor<br />

into an I/O pin <strong>of</strong> a circuit, with another pin, usually a supply or ground pin, tied to ground<br />

(Fig. 2.2a). According to the MIL-STD specification, the resulting waveform must have a<br />

rise time less than 10ns <strong>and</strong> a decay time <strong>of</strong> 150±20ns into a short-circuit load (Fig. 2.2b).<br />

The rise time is dependent upon the parasitic inductance <strong>and</strong> stray capacitance. For a<br />

HBM voltage <strong>of</strong> 1500V, the peak current would be approximately 1A. This model is<br />

meant to represent a discharge from a human finger into a pin <strong>of</strong> a circuit package. Several<br />

commercial testers which meet the military st<strong>and</strong>ard are available, e.g., the Hartley<br />

Autozap <strong>and</strong> IMCS 2400C ESD Sensitivity Test System, making HBM testing relatively<br />

simple.<br />

In a typical reliability test, all the I/O pins on a package are stressed with respect to all<br />

power <strong>and</strong> ground pins with both polarities <strong>of</strong> a given HBM voltage using an industrial<br />

tester. In addition, I/O pins may be stressed vs. other I/O pins, <strong>and</strong> supply pins may be<br />

stressed vs. ground pins. Current-leakage measurements at a specified reverse voltage<br />

(usually the operating voltage) are then performed on the same sets <strong>of</strong> pins. If a 2kV HBM<br />

test is performed on all pins <strong>of</strong> a package, <strong>and</strong> the resulting leakage current <strong>of</strong> all pins is<br />

below a certain level, say 1µA, then the IC is said to be resistant to 2kV HBM. Obviously,<br />

the HBM failure threshold is dependent upon the chosen failure-current definition. With<br />

the use <strong>of</strong> this model in <strong>design</strong>ing <strong>protection</strong> <strong>circuits</strong>, typical HBM failure thresholds have<br />

improved from 2kV in the early 1980s to about 6kV in the 1990s [2].<br />

The machine model (MM), also called the Japanese model due to its origin, is similar to<br />

the human-body model: a capacitor is charged to a certain voltage <strong>and</strong> then discharged

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