characterization, modeling, and design of esd protection circuits

5.4. Optimization 161
Qualitatively, we know from Fig. 5.56 and Fig. 5.60 that as DGS increases, the normalized
withstand current increases. Of course, transistor area and CDB also increase, but since the
normalized VHBM,ws increases, less total width is required for a certain withstand level. In
a similar manner, increasing the number of poly fingers requires lower W values to
achieve the same VHBM,ws , and if the increase in normalized VHBM,ws for lower W values
more than offsets the decrease in normalized VHBM,ws for higher n, less total area will be
required for the larger-n transistor.
To study these effects quantitatively, different values of DGS and n were set in the
Catalyst model for Lot 1 and W was adjusted to yield a VHBM,ws of 5000V. A lower limit
of six was set for the number of fingers since using fewer fingers would require a W much
larger than 50µm, which we deem undesirable. An upper limit of 6.2µm was placed on
DGS since the data shows that VHBM,ws saturates around this value and thus further
increase of DGS would only serve to increase area and capacitance. SGS was held
constant at 2.2µm.
Total source/drain diffusion area and CDB were calculated in each case for the minimum
W required for 5000V HBM. Calculations for the diffusion area, plotted in Fig. 5.61, show
that in the region of interest a reduction in area is always achieved by increasing DGS and/
or the number of fingers. Values of W range from 46µm for 4.2µm DGS and six fingers to
7.7µm for 6.2µm DGS and 10 fingers (the model boundaries were expanded to extrapolate
ITLP,ws for W < 25µm). Fig. 5.61 shows diminishing returns for area reduction as the
number of fingers is increased, especially for large values of DGS. Although CDB has a
perimeter dependence as well as an area dependence, its dependence on layout is very
similar to that of the area (including the diminishing returns), with values ranging from
1.4pF for 4.2µm DGS and six fingers to 0.56pF for 6.2µm DGS and 10 fingers. This
example illustrates that optimization of layout results in a 60% reduction in area and CDB from the worst-case design.
Other elements can also be considered during optimization. For example, gate delay may
be an issue for an RF circuit in which non-silicided, relatively resistive poly gates are used
on I/O circuits. In such a case an upper limit on finger width would need to be imposed,
and this is easily accomplished in Catalyst by specifying the range of values for the width
factor during the model definition phase. Also, each response can be assigned a target
value or designated as “larger is better” (e.g., ITLP,ws ) or “smaller is better” (e.g., Vsb ).