characterization, modeling, and design of esd protection circuits

3.4. Previous ESD Applications 73
In a slight departure, or perhaps combination, of the methods used by Amerasekera, Kuper
et al. [4] looked at J ⋅ E contours in the drain region of a MOSFET during a transient
simulation for devices with and without an LDD implant. In both drain profiles a hot spot
(peak in J ⋅
E)
forms deep in the junction, but their simulations predict that a shallow
LDD diffusion creates a second hot spot just under the gate which could lead to an “early
subsurface second breakdown.” This spot may heat up more quickly since it is directly
under the insulating gate, but it is more localized and thus will only slightly damage the
device. The authors conclude that soft failures in LDD structures, defined as a relatively
small increase in leakage (less than 1µA) due to a moderate ESD stress, may be a result of
the second hot spot seen in the simulations.
Diaz et al. [24] also used 2D electrothermal device simulations (TMA-MEDICI) to study
thermal breakdown, in this case for 0.6µm MOSFETs subjected to square-wave pulses. By
running transient simulations with different pulse lengths and monitoring peak device
temperature and drain voltage, they constructed simulated Pf vs. tf and It2 vs. tf curves
between about 50ns and 400µs (a broad range of the EOS spectrum) for devices with
various drain and source contact-to-gate spacings and compared the Pf vs. tf results to
experiments. Experimentally, failure was defined as “a change in the device leakage
characteristics,” while for simulations failure was defined by either a drop in the drain
voltage (second breakdown) or the maximum device temperature exceeding the melting
point of silicon (1688K), whichever occurred first. Only one thermal contact was placed
along the bottom of the simulated device, with a lumped thermal resistance and
capacitance to model heat conduction into the majority of the substrate that is not included
in the simulation space. Qualitative study of the temperature, potential profiles, and
current flow lines in the simulations suggested that device failure was due to second
breakdown in the drain depletion region. Peaks in the temperature profiles along the gate
oxide-silicon interface at the time of failure were very sharp and narrow for short times
but much broader with a large high-temperature region for long stress times. The variation
in peak temperature with failure time lead the authors to conclude that “it is not possible to
define the onset of device failure, particularly the onset of second breakdown, in terms of
a unique temperature value.”
Simulated Pf vs. tf curves were higher for devices with larger contact-to-gate spacing, in
qualitative agreement with experiments. However, the simulated failure power was too
low for failure times less than about 20µs and too high for times greater than 20µs. The