characterization, modeling, and design of esd protection circuits

32 Chapter 2. ESD Circuit Characterization and Design Issues
log(power)
P α 1/t
P α 1/√t
tc tb ta log(time)
P α 1/log et
P= constant
Fig. 2.12 A qualitative schematic of input power-to-failure vs. time-tofailure
predicted by an analytical thermal model.
metal contacts, which are good thermal conductors, and the distance between conducting
devices (as in a multiple-finger structure). Nevertheless, the model has been shown to
agree with experimental results to first order.
By carefully stepping the input voltage and using varying lengths of line, transmissionline
pulsing can be used to capture failure points (as in Fig. 2.10) and thus to define a
Pf vs. tf curve of an ESD protection circuit. The failure power level is the product of the
device voltage and device current at the point failure occurs (Vt2 and It2 ). Since each test
is destructive, several identical devices are needed to extract a curve. If the voltage drop
seen on the oscilloscope is second breakdown (thermal failure), there should be a
significant increase in the measured leakage current after the stress. As discussed in the
previous section, for very short pulse times a significant drop in voltage may not be
observed, in which case it is necessary to define failure as an increase in leakage current