characterization, modeling, and design of esd protection circuits

162 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
Diffusion Area / µm 2
3000
2000
1000
0
6 7 8
Number of Fingers
9 10
DGS (µm):
Fig. 5.61 Calculated minimum area of transistor source/drain diffusion needed for
5kV HBM protection for various DGS and number of fingers for Lot 1
with a SGS of 2.2µm.
After calculation of the models Catalyst will run an optimizing routine that attempts to
determine a set of factor values which will result in all responses meeting their targets.
The program will flag any condition (set of factors) for which a response exceeds
specification. This feature could prove useful if a model were added for CDM withstand
voltage and a circuit needed to be optimized for CDM as well as HBM performance.
5.5 Summary of Design Methodology
4.2 5.2 6.2
The methodology for the design of CMOS ESD protection circuits is effectively
summarized in block-diagram form in Fig. 5.62. First, a design space is defined and test
structures with varying layout dimensions are laid out for a given technology. Critical I-V
parameters and withstand currents are extracted through automated transmission-line
pulse characterization. These results are input along with the layout parameters to a
software program which generates empirical, second-order linear models relating HBM