characterization, modeling, and design of esd protection circuits

5.1. Methodology 151
needed to describe Rsb in a linear equation are DGS, SGS, 1/W, and 1/n. However, since
only two-factor interactions are represented in the model, a total-width factor, 1/(Wn),
must be included as a factor so that it may interact with DGS and SGS in the second and
third terms of Eq. (5.50). (An alternative would be to define W ⋅ Rsb or W ⋅n⋅ Rsb as the
response.) It is likely that not all layout factors will be needed for all responses. For
example, Vt1 and Vsb should have a very weak dependence on DGS and SGS since there
is very little potential drop at the low currents from which these responses are extracted.
Any of the model terms are easily turned off for any of the responses in the Catalyst
program. Model equations for other responses will be discussed in the next section.
Since either ITLP,ws or VHBM,ws data may be used to generate the withstand-voltage
model, we should consider which set of data is more valid or which will lead to more
accurate modeling. The main issue concerns the differences between the manual HBM
tester used to characterize the test structures and the large, automated testers (Verifier)
used to qualify circuits in the reliability laboratory. Even though both HBM testers meet
rise time, decay time, and ringing specifications for a short-circuit load (MIL STD 883C/
3015.7), differences in parasitic elements between different HBM testers lead to different
withstand voltages for a given device [71]. Specifically, a capacitance in parallel with the
DUT due to the test board, CTB , will initially charge to a voltage of Vt1 (refer to Fig. 5.54)
and then partially discharge into the device when the device snaps back. Assuming a
constant Vt1-Vsb difference, smaller structures will be more susceptible to early failure
due to this capacitive discharge. Values of CTB extracted from pulse waveforms and
SPICE simulations are 32pF for the Oryx manual tester and 20pF for the automated
Verifier tester. The large CTB of the manual tester is expected to affect the small test
structures and may explain why in Fig. 3.38 the HBM withstand value is lower than the
100ns and 75ns TLP withstand values for the single-finger structure but is more in line
with the TLP values for multiple-finger structures.
Although large test structures and the large protection circuits which are the target of the
modeling are less susceptible to tester parasitics, artificially low HBM withstand levels of
small structures are still a concern since they will skew the model. Therefore, ITLP,ws values will be used to create the models for HBM failure of IC protection circuits. The
models will predict ITLP,ws for a circuit, and this value will be multiplied by 1500Ω to
arrive at the predicted VHBM,ws .