characterization, modeling, and design of esd protection circuits

1.1. ESD in the Integrated Circuit Industry 3
1.1 ESD in the Integrated Circuit Industry
Electrical overstress is defined as damage to a product caused by exceeding data-sheet
maximum ratings [10]. EOS usually leads to gross damage in an integrated circuit
resulting from high-energy events such as electrostatic discharge, electromagnetic pulses,
lightning, or reversal of power and ground pins. EOS failure mechanisms fall into the two
broad categories of thermally induced failures and high electric-field failures [11]. The
duration of an EOS event may be anywhere from less than one nanosecond to one
millisecond and longer. Long EOS events can lead to damaged areas such as blown metal
lines, cavities in the silicon, or discoloration of silicon due to local heating with a
characteristic radius of 100µm or greater [10]. This damage leads to either a reduction in
IC performance (e.g., increased leakage current on one or more pins) or total circuit
failure.
The region of EOS phenomena with stress times of less than one nanosecond up to a few
hundred nanoseconds is known as electrostatic discharge. (Although EOS covers a large
range of phenomena including ESD, it is common to refer to the time range of 100ns and
less as the ESD regime and the time range greater than 1µs as the EOS regime, with a sort
of transition region from ESD to EOS between 100ns and 1µs.) ESD is a relatively rapid,
high-current event resulting from the high voltage created when electrostatic charges are
rapidly transferred between bodies at different potentials. ESD usually leads to relatively
subtle, localized damage sites extending less than 10µm.
As stated previously, there are two main dangers of ESD stress. One is the danger of gate
oxide dielectric breakdown due to the high voltage seen during an ESD event. In today’s
MOS technologies, gate oxides are on the order of 100Å thick, which given an SiO2 dielectric strength of 8X10 6 V/cm implies that a stress of 8V is enough to cause oxide
damage. In a typical CMOS technology, the thin gates of an input buffer are tied directly
to the input pin and thus are especially vulnerable to oxide breakdown. Dielectric
breakdown is also of concern within the protection circuits since thin-gate MOS devices
are commonly used. The other form of damage created by ESD stress is melting of
material due to Joule heating, which refers to the resistive heat generated by a current
moving through an electric field ( H =
J ⋅ E,
where H is the heat flow or power density).
If the high current of an ESD event is sufficiently localized in an area of high electric field,
thermal runaway (also called second breakdown) will result [12,13], leading to either