characterization, modeling, and design of esd protection circuits

10 Chapter 1. Introduction
conduction or insulation. Since device heating occurs as a result of the high currents in
ESD devices, and since second breakdown is a thermal process, lattice-temperature
modeling is an integral part of simulating ESD devices.
ESD simulations are also facilitated by a mixed-mode capability which allows circuit
simulation to be used in conjunction with device simulation. With this feature, devicesimulator
models of transistors are embedded in a SPICE-like circuit containing lumped
elements such as resistors, capacitors, and voltage sources. The circuit determines the
terminal voltages for the numerically simulated devices, which in turn provide the currents
for the SPICE circuit [29]. Simulations for the human-body model, machine model, and
other tests with complex inputs are easy to set up using the mixed-mode feature.
Several investigations have been reported on the use of 2D device simulation of EOS/ESD
phenomena, but most of these have been only qualitative (examining trends rather than
calibrating an actual process) or have focused on the EOS regime. For example, some
studies look at how variations in process parameters (junction depths and profiles,
substrate and diffusion doping levels) or layout parameters (gate length, drain contact-togate
spacing) affect a circuit’s ESD performance as measured by peak device temperature,
peak J ⋅ E (power density), or some other failure signature [24,32]. In two of these studies
quantitative agreement between simulated and experimental power-to-failure vs. time-tofailure
(Pf vs. tf ) curves was attained, but only for one region of the EOS/ESD spectrum
and only for one particular device. Other studies focus on topics such as the necessary
conditions for second breakdown [13], thermally induced low-level leakage [4], the effect
of pulse rise time on the trigger voltage [33], and the relative merits of using peak
temperature, peak J ⋅
E,
and second-breakdown trigger current as failure criteria in
simulated devices. A thorough discussion of past use of 2D simulation to study ESD is
given in Chapter 3.
Despite the number of publications on the application of 2D numerical device simulation
to ESD, there are significant applications of simulation which have remained unexplored.
In general, past studies have dealt mostly with thermal failure mechanisms and not with
dielectric failure or latent damage. Additionally, simulation has been used mainly as a
research tool and not as a design tool. This thesis investigates the viability of these new
applications by using simulation to create ESD models which accurately reflect the
electrical and thermal behavior of circuits designed in a state-of-the-art industrial CMOS