characterization, modeling, and design of esd protection circuits

24 Chapter 2. ESD Circuit Characterization and Design Issues
the substrate near the channel builds up due to the voltage drop across the substrate
resistance. This resistive drop, combined with possible drops in the drain diffusion and
contacts, is observed as a flattening in the I-V curve after the initial steep rise in current.
At the trigger point (Vt1 , It1 ) the potential in the channel reaches about 0.6V and the
source-substrate junction forward biases, turning on the parasitic bipolar transistor. The
suffix t1 stands for the time it takes to reach the trigger point, which is usually on the order
of 1ns but is very dependent upon the pulse height and rise time. Once this transistor turns
on the drain current consists mostly of electrons injected from the source, with a small
fraction of current still composed of II-generated electrons. Since a high electric field is no
longer needed to maintain the current level through impact ionization alone, the drain
voltage quickly drops to a level approximately equal to the BVCEO of the lateral bipolar
transistor. This “snapback” voltage, Vsb , is analogous to the hold voltage of a SCR device.
(Vsb is actually defined as the x-intercept of the line tangent to the I-V curve near the
snapback point.) To first order, the ratio of Vbd to Vsb is equal to β 1/n , where β is the
current gain of the bipolar transistor and n is a constant on the order of 5 [22].
In the snapback mode, the current rises along a line with slope 1/Rsb , where Rsb is the
dynamic snapback impedance or “on resistance.” Rsb is equal to the resistance of the
source and drain diffusions and contacts and is usually on the order of only a few ohms.
The device incurs no damage in the snapback mode unless the current level becomes high
enough to trigger thermal runaway (also called second breakdown), a positive-feedback
process. At the second-breakdown point (Vt2 , It2 ), which occurs at time t2 , a localized hot
spot forms in the region of high Joule heating ( J⋅E). As the temperature increases at this
spot, resistivity increases due to mobility degradation. However, the intrinsic carrier
concentration increases with temperature, and when it eventually meets and exceeds the
background doping level the silicon resistivity reaches a maximum and then decreases,
leading to an even higher current level and thus more heating. In the I-V curve, second
breakdown is characterized by a drop in the device voltage, a result of the negative
differential resistance. If there is sufficient power in the ESD pulse, enough current will
rush into the hot spot to raise the temperature above the silicon melting point, thus
damaging the device under stress through diffusion of dopants or formation of polysilicon
boundaries upon recrystallization. Beyond the second-breakdown point the current will
continue to rise very sharply (indicating very low device resistance) until a short circuit or
open circuit is formed by the thermal damage.