characterization, modeling, and design of esd protection circuits

140 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
optimize transistor layout for maximum HBM and/or charged-device model (CDM)
robustness, minimum clamping voltage, and minimum area [67]. Such work is of interest
because NMOS bipolar snapback will continue to be an effective ESD protection
mechanism in future technologies [68].
This chapter explores the use of empirical modeling of ESD protection-transistor
performance to optimize transistor layout and quantify the trade-offs in layout parameters.
As an example of these trade-offs, suppose that the ESD robustness of a previously
designed multiple-finger NMOS clamp must be increased, but there is only limited area
for expansion. A designer may choose to either add another poly finger to increase the
total transistor width or to increase the contact-to-gate spacing of the existing fingers,
thereby presumably increasing the robustness per unit width. It is not obvious which
option will yield the greater ESD withstand level, but accurate characterization of a large
design space over all critical layout parameters will lead directly to this answer. Chapters
3 and 4 demonstrated how electrothermal simulation is used to study the dependence of
ESD robustness on layout parameters, and other work has been published on this
application of two-dimensional [24,32] and even three-dimensional [69] simulation.
However, in all of these studies the simulations have been of simple circuit elements such
as single-finger transistors or diodes rather than of multifinger transistors, mainly because
of the greatly increased computation time and resources required for simulating large
devices. Therefore, while numerical simulation offers much understanding of the ESD
response of individual transistors, empirical modeling of an adequate layout design space
may be the best approach to characterizing and optimizing multifingered ESD circuits.
In the next section, an ESD-circuit design methodology is presented by reviewing the TLP
characterization of ESD test structures, investigating the correlation between TLP
withstand current and HBM withstand voltage, developing second-order linear models of
protection-transistor performance, and discussing the importance of identifying critical
ESD current paths in an integrated circuit. To verify the methodology, a model is extracted
from characterization of a 0.35µm CMOS process and its predicted responses are
compared to experimental HBM withstand levels of SRAM protection circuits. These
results are analyzed, and optimization of circuit layout is discussed. Conclusions are
drawn regarding the effectiveness of the methodology and how it may be enhanced in the
future.