characterization, modeling, and design of esd protection circuits

1.5. Design Methodology 11
process. After calibration of the 2D device models, a circuit’s susceptibility to dielectric
breakdown can be studied by monitoring the peak electric field in the gate oxide of the
MOSFET being protected (or of the MOSFET in the protection circuit) during a
simulation. Analysis of hot-carrier injection or non-catastrophic localized heating during a
simulated ESD stress may be correlated to low-level leakage (the latter phenomenon has
been addressed in [4]). Simulations of TLP experiments can be used to predict the critical
parameters of a transient I-V curve (breakdown voltage, snapback voltage, etc.) as well as
a power-to-failure vs. time-to-failure curve. Ultimately, 2D device simulation should be
used as a design tool to optimize the layout parameters of a protection circuit for ESD
robustness for a given CMOS process.
1.5 Design Methodology
Another approach to designing and optimizing protection circuits is to create models for
transient I-V and failure parameters using statistical design of experiments. By
characterizing a set of protection transistors with variations in layout, models can be
developed to describe the TLP I-V parameters, TLP withstand current, and HBM
withstand voltage as functions of transistor width, gate length, contact-to-gate spacing,
number of poly-gate fingers, and other layout parameters. (The withstand current or
voltage is defined as the maximum TLP current or HBM voltage, respectively, a structure
can withstand without incurring damage. Thus, the withstand level is always slightly
lower than the failure level.) A statistical design-of-experiments program is useful for
determining the minimum number of test structures needed and for extracting the model
equations. Once models are developed for a given technology, the performance of any
ESD circuit designed in that technology can be determined.
In Chapter 5 the design-of-experiments modeling approach is presented as the basis of a
complete integrated-circuit ESD design methodology. Second-order linear models are
used to relate the I-V and withstand parameters (responses) to transistor layout parameters
(factors). Other key parts of the methodology which are addressed include establishing a
correlation between TLP withstand current and HBM withstand voltage and identifying an
integrated circuit’s potential ESD discharge paths. An analysis of measured ESD
protection levels for a 0.35µm-technology SRAM circuit verifies that the methodology
can achieve quantitative predicition of ESD performance. Chapter 5 also discusses how
the second-order linear models may be used for protection-transistor optimization.