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characterization, modeling, and design of esd protection circuits

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Chapter 6<br />

Conclusion<br />

In the integrated-circuit industry, the ceaseless effort to decrease critical transistor<br />

dimensions in each new technology guarantees that the prominence <strong>of</strong> electrostaticdischarge<br />

will continue to grow. Devising ways to protect smaller transistors against ESD<br />

is just as important as determining how to process <strong>and</strong> manufacture them because a<br />

product with a high susceptibility to damage will not be widely accepted. As a result <strong>of</strong> its<br />

gradually increasing visibility over the last two decades, the problem <strong>of</strong> ESD is now dealt<br />

with by most IC manufacturers on several levels, from <strong>design</strong>ing on-chip <strong>protection</strong><br />

<strong>circuits</strong> to properly grounding the furniture <strong>and</strong> equipment in a fabrication facility to<br />

educating all personnel involved with wafer <strong>and</strong> package h<strong>and</strong>ling to minimize the<br />

potential for failure. Once an IC is packaged <strong>and</strong> shipped to a customer, however, the<br />

built-in <strong>protection</strong> circuit is the only means <strong>of</strong> defense against ESD damage. While circuit<br />

<strong>design</strong>ers have successfully created robust ESD <strong>protection</strong> for past technologies, a lack <strong>of</strong><br />

underst<strong>and</strong>ing <strong>of</strong> the mechanisms underlying ESD damage limited the amount <strong>of</strong><br />

transferrable knowledge from one technology to the next.<br />

With continually decreasing technology cycles, which are now less than two years in<br />

length, <strong>and</strong> the probable change in the prominent ESD failure mode from HBM-type<br />

damage to CDM-type damage in deep submicron technologies, ESD circuit <strong>design</strong>ers will<br />

no longer have time to start <strong>design</strong>s from scratch or follow a trial-<strong>and</strong>-error <strong>design</strong><br />

approach. Characterization <strong>and</strong> <strong>design</strong> methodologies, based on an underst<strong>and</strong>ing <strong>of</strong> the<br />

failure mechanisms behind ESD <strong>and</strong> models which accurately describe these mechanisms,<br />

must be implemented so that the critical features <strong>of</strong> a <strong>protection</strong> circuit can be determined<br />

<strong>and</strong> applied to future technologies. This chapter reviews the contributions <strong>of</strong> this thesis<br />

toward implementing such a methodology <strong>and</strong> proposes future work to be done in the area<br />

<strong>of</strong> ESD circuit <strong>characterization</strong>, <strong>modeling</strong>, <strong>and</strong> <strong>design</strong>.<br />

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