characterization, modeling, and design of esd protection circuits

4.1. Calibration Procedure 117
simulated. Such simulations were performed, but the results of these simulations are not
given until Section 4.3.
Mixed-mode simulations (Section 3.3) were used to model the TLP circuit shown in Fig.
2.14b, using a lumped 50Ω resistor between the square-wave voltage source and the drain
of the MOSFET (to simulate the transmission-line impedance) and a 50Ω shunt resistor
connected at the drain. Since the 100µm-wide test structures are robust enough that no
additional series resistance (Rs ) is needed in the TLP circuit, this resistance was left out of
the test setup and simulations. The rise time of the simulated square wave was set to 3ns,
the average rise time of the pulse in the TLP setup. Just as in the experimental setup, each
simulated TLP pulse width used to stress a structure has a unique height which will trigger
second breakdown. Thus, multiple simulations with different pulse heights must be run to
define a Pf vs. tf curve. Since the exact relationship between the input pulse height and the
time to failure is not known, the simulated square pulses are simply given very large
widths and a simulation is discontinued when failure is reached (determination of the
failure condition is discussed below).
As a starting point for determining the thermal boundary conditions, thermal electrodes
were placed coincident with the source, drain, gate, and substrate contacts just as they
were for the dc snapback simulations. This configuration implies that no heat transfer
occurs through the sides of the structure or the non-contacted areas on the top of the
structure. In the real structures, the substrate electrical contact is on the surface of the
source-side of the device, outside the defined simulation space. Therefore, the thermal
electrode overlapping the substrate contact along the bottom of the structure is not meant
to model the heat sink of the substrate contact itself but rather the heat sink of the entire
silicon substrate. As discussed in Section 3.1, by applying a lumped thermal resistance
and capacitance to the substrate thermal contact, the contact can be made to approximate
the thermal mass of the entire substrate. In simulations of very short ESD pulses, the
thermal boundary conditions are not important because the heating is very localized.
However, for longer stress times the high-temperature region extends a greater distance
and the thermal boundary conditions become more important.
In the initial transient simulations, a lumped thermal resistance of 10,000 K/W (a value
loosely based on a calculation by Diaz [24]) was placed on the substrate contact, and in
order to simplify the simulations no thermal capacitance was used. For simulations with