characterization, modeling, and design of esd protection circuits

2 Chapter 1. Introduction
and lower voltage tolerances. Use of lightly doped drains (LDDs) and silicide in newer
technologies exacerbates these problems. If the LDD diffusions are shallower than the
source/drain diffusions, then for a given current level there is a greater current density in
the LDD region, which means there is more localized heating and therefore a greater
chance of damage during an ESD stress [4-7]. This effect has been verified with
simulations as well as through failure analysis. Similarly, silicided source/drain diffusions
lead to current localization by concentrating current flow at the surface of devices as well
as reducing the ballasting resistance needed to distribute the current [6-9]. Finally, the
thinner gate oxides of newer MOS processes are more susceptible to high-field stress, i.e.,
dielectric breakdown.
Typically the design of ESD protection is an empirical, trial-and-error procedure in which
several variations of a circuit or types of circuits are laid out, processed, packaged, and
tested on a simple pass/fail basis. This approach is time consuming and does not facilitate
the evolution of protection circuits in future technologies. A better design methodology
includes a more complex testing technique and modeling of ESD circuit behavior in order
to provide understanding of the functionality of the transistors, diodes, and lumped
capacitors and resistors making up the circuit as well as to extract critical parameters of
the circuit. In conjunction with a relatively small array of test structures, proper modeling
can be used to design an optimum protection circuit as well as predict the performance of
similar circuits in next-generation technologies. Recent advances in two-dimensional
numerical device simulation have made possible the modeling of ESD events. These
simulations predict the device’s current-voltage response to an ESD stress and provide
analysis capabilities which suggest how and where a protection device will fail.
The focus of this thesis is on characterization, modeling, and design of ESD protection
devices in a state-of-the-art silicon CMOS technology using advanced testing techniques
and numerical simulation. MOS processes are studied because MOS is prominent in
today’s advanced technologies. This chapter is meant to create the context in which the
project task is undertaken by introducing the phenomena of ESD in the IC industry,
classical and novel characterization techniques, various CMOS protection circuits, and the
use of numerical device simulation to model ESD phenomena and design ESD protection
circuits. An outline of the thesis and a list of its contributions are presented at the end of
the chapter.