characterization, modeling, and design of esd protection circuits

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40 Chapter 2. ESD Circuit Characterization and Design Issues the I/O with the gate, source, and substrate tied to VSS . A PMOS device (M1) is placed between the I/O pad and VCC , with the drain connected to the I/O and the gate, source, and substrate tied to VCC . Normally, the input protection transistors are turned off because there is no conducting channel. Note that at the output the CMOS buffer doubles as the protection device. If a negative ESD pulse is incident between the I/O and VSS , the drainsubstrate diode of the NMOS device becomes forward biased and conducts the high current. If the pulse is positive valued, the NMOS device will conduct current in a parasitic bipolar-transistor mode, with the drain acting as collector, the substrate as base, and the source as emitter. A PMOS device behaves analogously during an I/O vs. VCC stress. If a protection MOSFET has a very short gate length, the device may actually turn on via punchthrough from source to drain rather than through snapback. This is a distinct possibility for devices built with minimal gate length in advanced technologies. A punchthrough device would have a lower Vt1 than that of a conventional protection MOSFET, but the snapback voltage would be the same because parasitic bipolar action would still dominate at higher current levels. In powered-up CMOS protection circuits, where VCC and VSS both form ac grounds and thus NMOS and PMOS protection circuits may be considered to be in parallel during a transient stress, it is often found that the NMOS absorbs the ESD energy regardless of pulse polarity [18, 21]. This means reverse breakdown of the NMOS device occurs faster than the forward turn-on of the PMOS drain-substrate junction for a positive ESD pulse and that the NMOS drain-substrate junction forward biases before PMOS snapback during a negative input pulse. This makes sense because the gain of the parasitic npn transistor in the NMOS device is much higher Input Output M1 V CC Bond pad M2 M2 Bond pad V SS M1 Fig. 2.16 CMOS input and output protection. The input protection transistors protect the thin gates of the input buffer, while the output protection transistors double as the output buffer.
2.3. Overview of Protection Circuit Design 41 than that of the pnp transistor in the PMOS device due to the lower diffusivity of holes, which means snapback occurs at a lower current for the NMOS device. PMOS transistors are still necessary, however, for protection of unconnected ICs. A diode created in a CMOS process has the same breakdown voltage as the MOSFET drain-substrate junction (neglecting curvature effects), but the MOSFET can be turned on more quickly and at a lower voltage by using a gate-bouncing technique. As seen in the MOSFET snapback curve, the transistor enters the low-voltage snapback mode when the drain voltage and current generate enough carriers through impact-ionization to forward bias the source-substrate junction. In a dc sweep the voltage Vt1 is usually two or three volts higher than the breakdown voltage, depending on the gate length of the MOSFET. During a transient pulse event, however, the maximum drain voltage can be held significantly below the dc Vt1 by coupling of the gate voltage to the input voltage through the drain-gate overlap capacitance. The gate bias is usually created by placing a resistor or tieoff transistor between the NMOS gate and ground (Fig. 2.17a) or between the PMOS gate and supply. An equivalent circuit of this setup is also shown in Fig. 2.17a. Given a ramp input described by Vin () t = V′ ⋅ t, the gate voltage as a function of time is Vgate () t = V′R gateCDG ( 1 – exp( – t⁄ RgateCDG) ) . (2.14) Given a gate resistance of 2000Ω, an overlap capacitance of 10fF, and a pulse edge of 100V/ns, the gate voltage should reach a value of V´RgateCDG = 2V during the rise of the pulse, enough bias to create MOS transistor action at the beginning of the pulse. Note that a higher pulse height with the same rise time (higher V´) will yield a higher gate voltage and thus a lower trigger voltage. After the initial bounce the gate bias will decay to zero as the drain voltage reaches a steady value. In protection transistors built using field oxide for the gate, the gate is often tied directly to the drain (input) to bias the gate. This can only be done because the threshold voltage of the field oxide device is higher than normal operating voltages and thus will not turn on during circuit use. Another advantage of the field-oxide device is that the thick oxide is much less susceptible to dielectric breakdown. Another gate-bounce technique is the relatively new method of dynamic gate coupling [41,43], in which a field-oxide device (FOD) is used to aid turn on of the primary thin-gate (TG) protection device (see Fig. 2.17b). The gate of the FOD is tied to the input pad (as is the thin-gate drain), with the drain of the FOD tied to the TG gate and the source grounded. In this circuit the TG gate is coupled to the input by the drain-gate overlap
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CHARACTERIZATION, MODELING, AND DES
Page 3 and 4:
Abstract For more than 20 years, su
Page 5 and 6: Acknowledgments This work could not
Page 7 and 8: Contents Abstract iii Acknowledgmen
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 55: 2.3. Overview of Protection Circuit
Page 59 and 60: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 105 and 106: 3.7. Simulation of Dielectric Failu
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3.7. Simulation of Dielectric Failu
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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