characterization, modeling, and design of esd protection circuits

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96 Chapter 4. Simulation: Calibration and Results the calibration philosophy and strategy are discussed in detail. This is followed by sections reporting the experimental and simulation results: the parameters Vt1 , Vsb , Rsb , and It2 (refer to Fig. 2.6) are extracted from TLP measurements and compared quantitatively with simulations, as are Pf vs. tf and If vs. tf failure curves. At the conclusion of the chapter, a design example of an I/O protection circuit based on the parametric results is given in order to demonstrate the applicability of transmission-line pulsing and device simulation to ESD circuit design. Due to limitation of time and resources, only NMOS circuits are studied in this chapter. It is critical to study these devices because it has been observed that the n-channel transistors in a CMOS protection circuit usually absorb the energy of an ESD pulse due to their lower turn-on time [18,21]. A complete circuit design certainly needs to include study of the PMOS transistors, but for purposes of proof of concept it is sufficient to concentrate on NMOS devices in this chapter. 4.1 Calibration Procedure Calibration of 2D device simulations to the AMD 0.5µm CMOS technology is broken up into three main steps. First, before I-V simulations can begin a 2D structure must be created to model the layout and process characteristics of the technology, including gate length, oxide spacer width, source/drain (S/D) contact-to-gate spacing, gate oxide thickness, and two-dimensional doping profiles. Next, this structure is used for simulations of standard drain, gate, subthreshold, substrate, and breakdown MOSFET characteristics to calibrate the mobility and impact-ionization (II) models. The model coefficients are adjusted until the simulated I-V curves match the experimental curves reasonably well. Finally, TLP-like simulations are calibrated to experimental TLP data. Further adjustment of the II coefficients is performed to match the trigger and snapback voltages while the thermal boundary conditions are set to yield simulated failure levels which parallel those of the actual devices. For proprietary reasons, most of the final model coefficient values and I-V curves will not be explicitly reported for the calibration procedure delineated below. 4.1.1 Structure Definition The 2D simulation structure was created based on SUPREM-IV [59] process simulations as well as secondary ion mass spectroscopy (SIMS), spreading resistance profile (SRP),
4.1. Calibration Procedure 97 and transmission electron micrograph (TEM) data with the goal of matching the actual structure dimensions and doping profiles. SUPREM-IV simulations were performed by AMD engineers and are based on the technology process flow. Although the 2D gridded structures generated by SUPREM-IV simulations are suitable for use in the device simulations, discrepancies were found between the simulated S/D junction depths and those extracted from SIMS and SRP data, which suggested that the junction depths are about 50nm greater than those of the SUPREM-IV simulations. Also, the simulated spacer width, which is explicitly defined in SUPREM-IV, is about 10nm wider than the spacer oxide seen in TEM photographs. Since there is no way to easily measure the S/D junction abruptness and LDD profile, the junction profiles calculated by SUPREM-IV were assumed to be correct. Calibrating the junction profiles can be accomplished by adjusting the parameters of the ion-implant and diffusion models in SUPREM-IV and iterating process simulation runs until more accurate results are attained, but this approach has two drawbacks. First, even a partial SUPREM-IV run, starting at the S/D implant, can take on the order of hours of simulation time. Second, the number of grid points needed for accurate process simulation is greater than the number needed for device simulation. Using an unnecessarily large number of grid points for device simulations is a large waste of time, and there is no way to eliminate grid points by “refining” the SUPREM-IV-generated structure file. Therefore, the approach taken in this calibration is to completely define the structure within the MEDICI device simulator. Doping profiles are defined analytically by specifying the peak and characteristic lengths of 2D Gaussian profiles. By using overlapping profiles, the 2D profile of the S/D, LDD, and channel regions can be fit reasonably well, as least within the uncertainty of the SUPREM-IV, SIMS, and SRP data. The gate oxide thickness is explicitly defined, while the spacer width is implicitly defined by the placement of the source-drain/LDD n + /n junction. When the structure is created, the number of grid points used is controlled by specifying how fine the grid should be in critical areas such as where the doping or electric-potential gradient is steep. Using a template input file to define the layout and profile parameters, MEDICI can create a MOSFET structure in less than five minutes, more than an order of magnitude faster than SUPREM-IV. A MEDICI-generated structure with three doping-profile grid refinements, or regrids, and three electric-potential regrids contains 589 grid points for a 0.5µm-gate-length structure with minimum contactto-gate spacing, while a 3.0µm structure has 1363 points. In contrast, the 0.4µm structure
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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Page 61 and 62: 2.4. Dependence of Critical MOSFET
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Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111: Chapter 4 Simulation: Calibration a
Page 115 and 116: 4.1. Calibration Procedure 99 conta
Page 117 and 118: 4.1. Calibration Procedure 101 4.40
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125 and 126: 4.1. Calibration Procedure 109 simu
Page 127 and 128: 4.1. Calibration Procedure 111 (a)
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133 and 134: 4.1. Calibration Procedure 117 simu
Page 135 and 136: 4.1. Calibration Procedure 119 volt
Page 137 and 138: 4.2. MOSFET Snapback I-V Results 12
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
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Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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