characterization, modeling, and design of esd protection circuits

12 Chapter 1. Introduction
1.6 Outline and Contributions
The purpose of this thesis is to demonstrate the power of transmission-line pulsing and 2D
numerical device simulation in the characterization, modeling, and design of ESD
protection circuits by expanding upon earlier work in these areas and introducing new
applications. Emphasis is placed on CMOS technology because it represents the leading
edge of the IC industry. Design focuses on layout parameters because the ESD circuit
designer is usually given a process with which to work and has no control over the
junction depths, junction profiles, doping concentrations, etc. Among the contributions of
this thesis are
• a quantitative analysis of the ability of 2D numerical device simulation to model
experimental I-V and Pf vs. tf curves of submicron-technology protection devices in the
ESD regime and a demonstration of how simulations can be used to design ESD
circuits in a state-of-the-art technology
• an investigation of the use of 2D simulation to study dielectric ESD failures and latent
ESD damage
• a demonstration of the unique ESD characterization abilities of the transmission-line
pulsing method
• a methodology for layout design and optimization of CMOS ESD protection circuits
• an example of the practical application of Stanford’s curve-tracing program
• a calculation, based on an analytical thermal model, of the accuracy of 2D device
simulation in predicting thermal failure for a range of ESD pulse times
• confirmation that transmission-line pulse and human-body model withstand levels can
be correlated over at least a small transistor design space.
Chapter 2 addresses characterization and design issues of ESD circuits, starting with a
detailed discussion of the classical industrial models used to qualify ESD robustness and
of the applications of transmission-line pulsing. Next, the functionality of some standard
protection circuits is described, including a physical explanation of the transient I-V curve
of a MOSFET. The critical parameters of this I-V curve and their dependence on process
and layout variables are presented, followed by a discussion of ESD circuit design
methodology.