characterization, modeling, and design of esd protection circuits

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36 Chapter 2. ESD Circuit Characterization and Design Issues (a) (b) Power Supply + V in - + V in - R i =1MΩ R L =50Ω R L S R L R S R S V dev DUT DUT Voltage Probe Scope Probe Transmission Line R L =50Ω Fig. 2.14 (a) Advanced TLP schematic: a series-parallel resistor combination has been added to enhance current resolution. A current probe is now used to directly measure the device current on the oscilloscope. (b) Equivalent circuit of the TLP setup. Now, just before and just after snapback, V in is approximately 2V t1 , so at snapback Idev = ( Vt1 – Vsb) ⁄ ( RS + RL ⁄ 2) . (2.13) and we see that RL is replaced by RS + RL ⁄ 2. Using a value of RS = 300Ω, the current resolution is now 18mA. An added benefit of the 50Ω shunt resistor is that it will absorb all the pulse energy and prevent reflections when the impedance of the DUT is high. In the AMD setup a special high-frequency jig with insulated wires running from BNC connectors to the pins of a low-insertion-force socket was built to minimize noise during measurements of test circuits prepared in dual in-line packages. Additionally, chip resistors are used for the resistor network and all connections are kept as short as possible to minimize parasitic inductances which alter the shape of the measured voltage and I dev Current Probe I dev = Vin - 2Vdev RL + 2RS
2.3. Overview of Protection Circuit Design 37 current profiles. The switch S is a normally closed, single-pull double-throw vacuum relay which is opened and closed by applying and disabling a 12V power supply, respectively. During a stepped-stress experiment, a leakage measurement between input and ground is taken after each pulse by switching the input from the transmission line to an ammeter in series with a VCC supply (not shown in Fig. 2.14). This switching is done with a voltagecontrolled 10GHz coaxial relay placed between the probes and the DUT input. Currently, an HP3457A multimeter with 1nA resolution is used for leakage measurements, but this will eventually be replaced by an HP4145 parametric analyzer with 1pA resolution. All instruments and power supplies are controlled by a personal computer through either a National Instruments AT-GPIB/TNT IEEE-488 card or a National Instruments PC-DIO-96 digital I/O board. National Instruments’ LabVIEW software package is used to automatically run a TLP experiment on a test structure and store all I-V and leakage data from initial device breakdown through device failure. A built-in oscilloscope function which measures the average height of a waveform in a gated region facilitates the automatic extraction of the device voltage and current resulting from each input pulse. 2.3 Overview of Protection Circuit Design This section is not meant to provide an exhaustive review of all types of on-chip protection but rather to introduce some basic concepts. A thorough discussion of on-chip protection is presented in [34]. Any I/O protection circuit should provide a low-impedance path from input to supply during an ESD event to absorb current but provide a very high impedance during normal operating conditions so as not to affect circuit performance, e.g., through increased leakage current or parasitic capacitance. Additionally, an ESD circuit should clamp input voltages at a safe level, i.e., below the dielectric breakdown voltage of a thin gate transistor. The dielectric threshold electric field is actually time dependent: it must be held across an oxide for a certain length of time before the oxide breaks down, as measured by leakage current [40]. The time to breakdown is lower for a higher stress field. Although the consequences of this time dependence on ESD protection ability are important, for simplicity we will assume that the voltage across a thin gate must not exceed some critical level for any amount of time. When designing ESD protection circuits, there are some important differences to consider between input protection and output protection. While the high-impedance input pads of a CMOS chip are connected to the thin gates of the input buffer transistors, the low-
Page 1 and 2: CHARACTERIZATION, MODELING, AND DES
Page 3 and 4: Abstract For more than 20 years, su
Page 5 and 6: Acknowledgments This work could not
Page 7 and 8: Contents Abstract iii Acknowledgmen
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51: 2.2. Transmission Line Pulsing 35 F
Page 55 and 56: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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