characterization, modeling, and design of esd protection circuits

158 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
from Fig. 5.60, the condition for which the model predicts ITLP,ws < 0 for large DGS is
< 0.013µm-1 1 ⁄
W
(W > 76µm). This nonphysical aspect of the model is a result of
having to extrapolate beyond the design space, which does not cover the large DGS-large
W corner, and could be corrected by expanding the design space to this corner.
Fortunately, the largest DGS of any of the SRAM protection circuits is 4.2µm, so the
model predictions for the circuits of interest are accurate.
5.3.2 SRAM Model Prediction
As mentioned previously, HBM withstand levels of an IC cannot be predicted unless the
stress current paths are known. The SRAM test circuit used for this study has only one
VCC and one VSS supply, which simplifies the ESD analysis. For reasons discussed in
Section 5.1.4, I/O vs. VSS failures are expected to occur in the NMOS pull-down circuit,
while I/O vs. VCC and VCC vs. VSS failures are expected to occur in the VCC-VSS supplyclamp
circuit (refer to Fig. 5.59). The observed failure mode for I/O vs. VSS SRAM
testing is pin leakage to VSS , while the failure mode for I/O vs. VCC and VCC vs. VSS is
increased stand-by current. These failures indicate damage to pull-down and supply-clamp
circuits, respectively, confirming the expected failure mechanisms. Emission microscopy
was also attempted for failure analysis but no emission sites were seen due to the metal
busing over the pull-down and clamp circuits.
Although the pull-down protection circuits of bi-directional (“Full I/O” in Table 5.2) and
input-only (“Input”) I/O pins have the same layout parameters, separate HBM stressing of
each type of I/O results in higher withstand voltages for the input-only pins. For the inputonly
pull-down circuits, all 10 gate fingers are tied to a dummy inverter which provides
the needed gate bounce to reduce the trigger voltage. For the bi-directional I/Os, however,
half of the gate fingers are tied to a dummy pre-driver while the other half are driven by
internal circuitry, i.e., they drive the output. Since the two pre-drivers are of different size
and thus offer different degrees of gate bounce, we hypothesize that only half of the
fingers are turning on due to different trigger voltages, which would explain why the bidirectional
I/Os are less robust than the input-only I/Os. For modeling purposes, then, an n
value of 10 is used for the input-only stress while a value of 5 is used for the bi-directional
I/Os. (Actually, an n value of 1 is used in determining the normalized VHBM,ws because in
the layout every other finger is tied to the same pre-driver and thus the five fingers are