characterization, modeling, and design of esd protection circuits

2.3. Overview of Protection Circuit Design 39
Input Output
D1
V CC
(a)
Bond pad D2
D2 Bond pad
(b)
Bond pad
V CC
V SS
R diff
VSS Fig. 2.15 (a) ESD diode protection circuit in a CMOS technology; (b)
use of a series resistor in combination with diode protection. A
diffused resistor has a distributed resistance and also forms a
distributed diode.
using larger diode areas, but this takes up valuable chip real estate and may increase the
parasitic capacitance to a level no longer negligible compared to the input-gate capacitance,
thus degrading high-frequency performance. Reverse diode resistance can also be
decreased if a diode with a smaller depletion layer can be processed, but the reduction of
the depletion layer again implies a higher capacitance. Another limitation of diodes is that
the breakdown voltage itself may be higher than the dielectric threshold of today’s thin
gate oxides. Finally, a diode often cannot break down quickly enough to protect a circuit
from a fast-rising transient pulse such as that created by the charged-device model.
Fig. 2.16 shows a CMOS-transistor protection scheme. These devices, which can be either
thin-gate or thick-gate (field) transistors, have the advantage of being built using the
standard chip process without additional implant or masking steps. (One exception is that
a resist mask which blocks the silicide deposition may be added to increase the drain-togate
and source-to-gate resistance.) The drain of the NMOS device (M2) is connected to
D1
D2
Input
D1