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characterization, modeling, and design of esd protection circuits

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4.3. Device Failure Results 127<br />

already discussed in Section 1.1 as well as by Polgreen [8]. In the TLP tests, failure is<br />

defined as the point at which device leakages exceeds 1µA, while in the thermal-box<br />

model failure is defined as the onset <strong>of</strong> second breakdown. A certain current density is<br />

needed to cause a device to enter second breakdown, but widespread damage does not<br />

follow instantaneously in narrow devices because there is not enough total energy in the<br />

TLP pulse, <strong>and</strong> consequently narrow structures must be stressed with higher pulses than<br />

predicted before damage is severe enough to create microamp leakage. Of course, the<br />

absolute current to failure <strong>and</strong> power to failure increase with device width, but note that as<br />

the width increases beyond 50µm, the failure current per width levels <strong>of</strong>f (Fig. 4.49b)<br />

while the normalized failure power continues to decrease (Fig. 4.49a), indicating that the<br />

device voltage at failure, Vf , decreases with width. The decrease in failure voltage with<br />

width is explained by the fact that the snapback resistance, which is roughly inversely<br />

proportional to the width (Fig. 4.46), decreases with width more rapidly than the failure<br />

current increases with width. In Section 2.4 <strong>and</strong> Table 2.1, the width was predicted to have<br />

no effect on Vf (Vt2 ), but in Section 2.4 it was assumed that the failure current scales<br />

directly with width, which is not the actual case. It would be beneficial to test even wider<br />

structures to determine if there is a point at which the normalized power to failure levels<br />

<strong>of</strong>f.<br />

In Section 4.1.4, the 100µm-wide structure was used for calibration <strong>of</strong> thermal failure<br />

because microamp leakage was almost always created the first time second breakdown<br />

was captured on the oscilloscope <strong>and</strong> thus there was no ambiguity in defining the failure<br />

level. However, as seen in Fig. 4.49b another advantage <strong>of</strong> using wide structures for<br />

calibration is that the measured failure current is proportional to device width for wide<br />

devices <strong>and</strong> therefore more amenable to 2D simulation. In contrast, according to the<br />

thermal-box model the intrinsic error between predicted 2D <strong>and</strong> 3D failure power (or<br />

failure current) is independent <strong>of</strong> device width (Fig. 3.33). Again, the conflicting results<br />

are due to the different concepts <strong>of</strong> failure <strong>and</strong> underline the importance <strong>of</strong> consistently<br />

defining failure in experiments <strong>and</strong> simulations.<br />

Experimental <strong>and</strong> simulated failure power vs. contact-to-gate spacing for 50/0.75µm<br />

structures subjected to 200ns TLP stressing are compared in Fig. 4.50. As just stated, the<br />

experimental failure level is defined as the power needed to create microamp leakage, but<br />

for 200ns pulses this level usually coincides with the power-to-second breakdown. In the<br />

simulations failure was defined, as described in Section 4.1.4, either by the time at which

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