characterization, modeling, and design of esd protection circuits

142 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
are the trigger voltage (Vt1 ), snapback voltage (Vsb ), snapback resistance (Rsb ), and
second-breakdown (thermal-runaway) point (Vt2 , It2 ). For TLP widths on the order of
100ns, device failure usually follows instantaneously when the second-breakdown point is
reached, in which case It2 is equivalent to the failure current, Ifail . Failure is defined as
1mA of leakage current when the drain is biased at the technology supply voltage, VCC .
Tracking the I-V response of a structure is just as important as determining the failure
current because dielectric failure at an input gate oxide will occur if a protection circuit’s
clamping voltage becomes too high.
Section 2.2 described in detail the equivalent circuit of the TLP setup, the equipment used
to monitor the voltage, current, and leakage of the device under test (DUT), and the
automated software used to extract the TLP I-V curve of the DUT. For the testing
discussed in this chapter, the step size of the transmission-line charging voltage is set to
yield current increments of about 30mA per step. In addition to characterizing structures
with TLP, test structures are also stressed with HBM pulses using an Oryx Model 700
manual ESD tester. As with TLP, the drain is subjected to pulses with the source,
substrate, and gate grounded, but in this case three positive and three negative pulses are
applied at each voltage level to parallel the procedure of circuit-qualification HBM testing.
The HBM withstand voltage (the maximum HBM voltage a structure can withstand
without incurring microamp leakage) is obtained by step stressing the structure in 50-volt
increments until the device fails. These 50-volt increments are equivalent to about 33mA
increments in peak pulse current since the HBM pulse is discharged through a 1500Ω
resistor. Further comparison of the TLP and HBM test methods will be made in the next
subsection. To verify that step stressing does not introduce stress-induced hardening, i.e.,
an artificial increase in withstand voltage due to a burn-in type phenomenon, some
structures were also stressed at a single voltage around the failure point determined by the
step stressing. Results showed no effect of previous stresses on the failure level of a
structure.
To characterize a process, TLP and HBM tests are run on a set of test structures with
varying layout parameters, contained on dedicated tiles of a test chip. An example of a
multiple-finger test structure is shown in Fig. 5.55 and defines the critical layout
parameters: poly finger width (W), gate length (L), drain and source contact-to-gate
spacing (DGS and SGS), and number of poly fingers. As discussed in Section 2.4, in fully
silicided processes varying CGS has little effect on ESD performance since the silicide