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characterization, modeling, and design of esd protection circuits

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2.2. Transmission Line Pulsing 19<br />

industry wide over a number <strong>of</strong> years. As long as a packaged product is resistant to HBM<br />

tests up to some level <strong>of</strong> stress, say 4kV, then it is considered to be reliable from an ESD<br />

st<strong>and</strong>point. However, as the result <strong>of</strong> an emphasis on preventing ESD damage from human<br />

h<strong>and</strong>ling during production, e.g., by ensuring proper grounding <strong>of</strong> personnel <strong>and</strong><br />

equipment <strong>and</strong> by using ESD-controlled workstations, the human-body model no longer<br />

represents the dominant failure pattern in the industry [10].<br />

Today the main area <strong>of</strong> concern is shifting to the charged-device model (CDM), which<br />

introduces a different failure mode from that <strong>of</strong> the HBM <strong>and</strong> MM. In this model,<br />

electrostatic charge builds up on a chip due to improper grounding <strong>and</strong> then discharges<br />

when a low-resistance path becomes available. It is meant to simulate ESD phenomena <strong>of</strong><br />

packaged ICs during manufacturing <strong>and</strong> assembly. For example, a package connected to<br />

the ground pin may be inductively charged up as it is transported along a conveyor belt,<br />

then discharged through any pin touched by a metal h<strong>and</strong>ler or test socket [18]. The<br />

characteristic rise time <strong>of</strong> a CDM pulse is 1ns or less, with a peak current <strong>of</strong> several amps.<br />

Since the turn-on time <strong>of</strong> MOS <strong>protection</strong> <strong>circuits</strong> is on the order <strong>of</strong> 1ns, high voltages<br />

have a chance to build up across oxides during a CDM event. Thus, damage to thin oxides<br />

(<strong>of</strong> the <strong>protection</strong> device as well as the internal gates being protected) is the signature<br />

failure <strong>of</strong> CDM events, in contrast with the thermal failure signature <strong>of</strong> the HBM.<br />

A typical CDM test consists <strong>of</strong> placing a charge on a substrate (ground) pin using a<br />

voltage source, then disconnecting the voltage source <strong>and</strong> connecting a different pin<br />

through a low-inductance, low-impedance, 1Ω probe to ground (Fig. 2.4). In another<br />

method referred to as the field-induced model (FIM), a charge is induced on the substrate<br />

by placing the chip on a conducting surface, then discharged through a pin via a lowimpedance<br />

probe. Like the machine model, the CDM has no established st<strong>and</strong>ard, <strong>and</strong><br />

there is a need for further underst<strong>and</strong>ing <strong>of</strong> the phenomena underlying the model. The<br />

higher ESD sensitivity <strong>of</strong> shrinking oxides <strong>and</strong> reduced susceptibility to human h<strong>and</strong>ling<br />

will provide the incentive for continued development <strong>of</strong> the CDM.<br />

2.2 Transmission Line Pulsing<br />

It is obvious from the discussion <strong>of</strong> the classical <strong>characterization</strong> models that a single type<br />

<strong>of</strong> test or figure <strong>of</strong> merit is not sufficient to guarantee robustness against all EOS/ESD<br />

failures. It is possible for a circuit to pass one type <strong>of</strong> test, say the human-body model,

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