characterization, modeling, and design of esd protection circuits

22 Chapter 2. ESD Circuit Characterization and Design Issues
To prevent multiple reflections when the device impedance is less than 50Ω, a diode and
resistor are placed on the end of the line opposite the device under test (DUT).
2.2.1 MOSFET Snapback I-V Curve
Transmission-line pulsing is useful for garnering several pieces of information about an
ESD protection circuit. The most obvious application is the extraction of transient currentvoltage
(I-V) curves of protection devices, especially MOSFETs. By pulsing a circuit with
a series of increasing input voltages and plotting the resulting device voltage and current
points, a characteristic I-V curve is produced. Unlike a conventional curve tracer, which
would cause destructive heating with its relatively long stepped stresses, the short pulses
of the TLP method allow the extraction of I-V points up to very high current levels
without causing thermal damage. Of course, the time between stresses should be enough
to allow complete thermal dissipation--one or two seconds is more than enough. The
transient I-V curve of a protection device is very informative because it reveals what the
device is doing during an ESD stress. Critical parameters of the device such as the turn-on
voltage, snapback voltage, and second-breakdown trigger current (all described below)
can be read directly from the curve. Although the square-wave input does not precisely
model any probable ESD event, parameters of the resulting I-V curve can be correlated
with susceptibility to “real” ESD stresses and with tests such as the HBM [23].
Since MOSFETs in ESD protection circuits operate in an unconventional manner, it is
necessary to discuss the device’s complex I-V curve and the underlying physics to see the
advantages of transmission-line pulsing analysis as well as to appreciate the device’s
usefulness. Conduction of ESD current does not occur through MOS transistor action but
rather via the lateral bipolar transistor in which the drain, channel, and source act as the
collector, base, and emitter, respectively. The qualitative I-V characteristic of an NMOS
protection device subjected to a positive ESD pulse is shown in Fig. 2.6. In the setup a
voltage pulse is incident upon the drain of the device with gate, source, and substrate
grounded. As the input pulse rises, the drain voltage rises until the drain-substrate junction
breaks down due to impact-ionization (II) and significant current begins to flow from drain
to substrate. This breakdown voltage, denoted BVDSS or Vbd , is defined as the voltage at
which the drain current reaches a critical value, usually 1µA. The substrate current
consists of II-generated holes flowing from the junction to the substrate contact.
Additionally, some holes will flow to the source. As this current increases, the potential of