characterization, modeling, and design of esd protection circuits

4.4. Design Example 135
reached, the current in a TLP pulse remains at its peak value for the entire 200ns and thus
applies a greater stress. Since the robustness of the test structures is known in terms of mA
of current per µm of device width, once a structure is chosen the total width required is
simply the peak HBM current, 2.67A, divided by the mA/µm.
To choose an appropriate structure, a compromise must be reached between the goals of
good EOS performance and minimal device area. Fig. 4.53b in the previous section shows
that while increasing contact-to-gate spacing does not seem to improve device robustness
for stress times on the scale of the human-body model, it definitely improves robustness
for longer times, i.e., in the EOS regime. However, increasing CGS increases the total
device area, so it cannot be made arbitrarily large. As seen in Fig. 4.51, the gain in failure
current with increased CGS seems to level off at about 6µm CGS for 200ns pulses, and
Fig. 4.53b shows that this is also true for longer stress times. Thus, a trade-off between
EOS performance and device layout area is made by selecting a contact-to-gate spacing of
5µm. Section 4.1.3 reported vales of 11.8V for Vt1 and 8.2V for Vsb for all the test structures.
In Fig. 4.45, Rsb for a 50µm-wide, 5µm-CGS structure is interpolated as 8.3Ω.
Neglecting the nonlinear dependence of Rsb on the inverse device width, Rsb X W will be
assumed to have a constant value of 8.3 X 50 = 415Ω-µm for design purposes. From Fig.
4.53b, the interpolated average failure current of a 50/0.75µm device with 5µm CGS is
641mA, or 12.8mA/µm of device width. Fig. 4.49 indicates that the failure current density
for a 50µm structure is approximately constant for fingers wider than 50µm, so the 50µm
value will be used regardless of the finger widths chosen. Thus, the total 5µm-CGS device
width needed to sustain 2.67A peak HBM current is 208µm.
The value for total required width assumes not only that the failure current density per
micron is independent of width but also that when the multiple fingers are placed side by
side, each will act exactly as if it were a single-finger structure. This second assumption
will not hold for high stress currents because the heat which dissipates from a finger into
the substrate in all directions will reduce the heat dissipation in neighboring fingers, thus
lowering the effective current per width the device can withstand before failure. This
problem is more severe for longer (EOS) stress times than for shorter (ESD) stress times.
To quantify the effects of heating in adjacent fingers, multifinger test structures need to be
created. For the present case, the fact that there is more energy in a 200ns TLP pulse than
in an HBM pulse of the same peak current will be used to justify the calculations. Also,
the calculated required width of 208µm will be increased to 250µm. The total device area